请问内存控制器/ ddr（1 2或3）连续带宽有多大？

您需要了解，带宽将取决于许多参数：您使用的内存类型，内存总线的宽度，实例化的MCB数量，数据访问模式是否随机等。
要回答关于最大带宽的假设性问题，请考虑以下问题：
1）您在x16 800Mbps模式下有4个MCB工作的芯片
2）你写入连续的内存块，没有任何随机访问
3）你只写入内存
那么最佳情况内存带宽（上限）将是4x16x800 = 51200Mbps = 6400兆字节/秒。
好？
在原帖中查看解决方案



以下为原文

You need to understand, that the bandwidth will depend on many parameters: what kind of memory you use, how wide is the memory bus is, how many MCBs you have instantiated, whether your data access pattern is random or not, etc.
 
To answer your hypothetical question about maximum bandwidth, consider the following:
1) You have a chip with 4 MCBs working in x16 800Mbps mode
2) You write to contiguous blocks of memory, no random access whatsoever
3) You only write to memory
 
Then the best case memory bandwidth(upper bound) will be  4x16x800=51200Mbps = 6400 Megabytes per second.
 
OK?
View solution in original post

当你看到像“800Mbps DDR2”这样的东西时 - 他们说时钟是400MHz，每个位都在时钟的两个边沿传输数据。
带宽能力将是总线宽度乘以总线宽度。
有效带宽可以低得多，并受控制器算法的影响（例如，我们在Virtex-5上使用最近最少使用的算法，可以保持多个存储体打开并改善内部延迟），访问模式，方向，突发长度，刷新注意事项
等
您将在V6控制器上看到其他功能，以增加有效带宽。
BT



以下为原文

你好
同意你的表现与情况有关，这是双倍数据率，但引用了斯巴达6产品简报。
“集成内存控制器只有具有集成内存控制器的低成本FPGA才能支持DDR，DDR2，DDR3和LPDDR 
数据速率高达800Mbps（峰值带宽12.8Gbps）“
具有128位接口的每秒800兆位，即每个引脚上的平均时钟速度约为3 MHz， 
对于时钟为400 + MHz的内存，数据是双倍数据速率，这不是很慢吗？



以下为原文

Hi
 
Agree with you in that performance is situation related, and it's double data rate, but quoting from the spartan 6 product brief.
 
"integrated Memory Controllers               Only low-cost FPGA with integrated memory controller blocks
                                                                DDR, DDR2, DDR3, and LPDDR support
                                                                Data rates up to 800Mbps (12.8Gbps peak bandwidth)"
 
So is that 800 Mega bits per second with a 128 bit interface, i.e. an average clock speed of around 3 MHz on each pin,
   is that not very slow for a memory that has a  clock of 400 plus MHz, and data is double data rate ?
 
 

每个引脚上的3MHz确实会非常慢。
但是内部和外部接口似乎存在一些混淆。
S6 MCB提供4位，8位或16位的外部接口。
这就是12.8Gbps峰值带宽的来源。
在内部，您必须以更慢，更宽的单数据速率接口运行结构后端，以处理FPGA内部的数据。
MCB的后端是FPGA内部的32位，64位或128位数据总线。
“MCB用户指南”中的更多详细信息：
http://www.xilinx.com/support/documentation/spartan-6.htm(Spartan-6文档）
BT



以下为原文

3MHz on each pin would indeed be very slow. But there appears to be some confusion on the internal and external interfaces.
 
The S6 MCB offers an external interface of 4, 8, or 16-bits. That is where the 12.8Gbps peak bandwidth is coming from.
Internally, you have to run the fabric back-end at a slower and wider single-data rate interface to handle the data inside the FPGA. The backend of the MCB is a 32, 64, or 128-bit data bus inside the FPGA.

More details on in the MCB User Guide:
http://www.xilinx.com/support/documentation/spartan-6.htm (Spartan-6 Documentation)
 
bt

谢谢timpe，
是的，你引用的网络链接是我从中得到的信息。
是的，在FPGA内部，我们运行的是单数据速率，而不是DDR，我们考虑到FPGA内部的数据速率与外部相比较慢。
但这里没有回答的问题是Xilinx接口的保证连续数据速率，每个引脚只有3 MHz左右？ 
这不可能，可以吗？
简化问题，具体而非一般。
使用最快的Spartan 6内置内存控制器，使用我能得到的最快的DDR 3芯片，可以进入或退出DDR 3内存的持续数据速率。



以下为原文

thank you timpe,
 
yep, the web link you quote is where I got the info I quote to you from.
 
 Yep agree, inside the FPGA we run single data rate, not DDR, and we run wide to account for the slower data rate inside the FPGA compared to the out side.
 
 but your not answering question here, is the guaranteed continuous data rate of the Xilinx interface as stated only around 3 MHz per pin ? 
   this can't be, can it ? 
 
Simplify  question, specific, not general.
 
What sustained data rate can I get into or out of a DDR 3 memory, using the fastest Spartan 6 built in memory controler, double chanel, using the fastest DDR 3 chips I could get. 
 

我不清楚你在哪里得到“每个引脚3MHz”唯一的引脚是外部接口，它们每个可以传输高达800Mbps。
因此，对于16位接口，整个MCB的峰值带宽为12.8Gbps。
后端接口将运行得更慢，更宽，并且SDR。
我没有最终的特征#s可用。
但是，当你考虑持续吞吐量时，我看到的初步数字显示出非常好的有效利用率。
它显然取决于存储器的类型（例如DDR2，DDR3或LPDDR），传输类型，方向等。例如，效率随着随机寻址和较短的突发模式而下降。
这些数字不是正式的，但对于DDR3I，请参见以下范围：
最佳情况：突发写入高（95％+），长度32
低至：大约50％随机操作，突发长度在4到16之间
这里显然有一系列的操作。
即使效率为50％，您仍然可以获得6.4Gbps的有效带宽。
你在哪里获得每针3MHz的频率？
BT
消息由timpe在06-30-2009 02:29 PM编辑



以下为原文

It isn't clear to me where you keep getting this "3MHz per pin" The only pins are the external interface and they can transfer up to 800Mbps each. So for a 16-bit interface, that would be a peak bandwidth of 12.8Gbps for the entire MCB. The back-end interface will be running slower, wider, and SDR.
 
I don't have the final characterization #s available. But the preliminary numbers I'v'e seen show very good effective utilization when you consider sustained throughput. It obviously depends on the type of memory (e.g. DDR2, DDR3, or LPDDR), the type of transfers, direction, etc. For example, the efficiency drops with random addressing and shorter burst patterns. These numbers are not official but for DDR3 I see a range of:
best case: high (95%+) for burst writes, length 32
down to: around 50% with random operations with a burst length between 4 and 16
There are obviously a range of operations in between here.
Even at 50% efficiency, you still have 6.4Gbps of effective banwidth.
 
Where are you getting this 3MHz per pin?
 
bt
 
 
Message Edited by timpe on  06-30-2009 02:29 PM

你好
引用产品简介。
“集成内存控制器只有具有集成内存控制器的低成本FPGA才能支持DDR，DDR2，DDR3和LPDDR 
数据速率高达800Mbps（峰值带宽为12.8Gbps） 
具有独立FIFO的多端口总线结构，以减少“ 
所以要明确的是，您所说的Spartan 6产品简介中每秒800兆位的数据是Spartan 6每个外部引脚的最大峰值数据速率吗？



以下为原文

Hi
 
 to quote the product brief.
 
" Integrated Memory Controllers               Only low-cost FPGA with integrated memory controller blocks
                                                                  DDR, DDR2, DDR3, and LPDDR support
                                                                  Data rates up to 800Mbps (12.8Gbps peak bandwidth)
                                                                  Multi-port bus structure with independent FIFO to reduce "
 
 
 so to be clear, you are saying the 800 Mega bit per second quoted in the Spartan 6 product brief is the maximum peak data rate per external pin of the Spartan 6 ?
 
 
 

是。
800Mbps * 16 = 12.8Gbps
显然，x8或x4的较窄配置将是相应最大带宽的一半或四分之一。
我在上面概述了现实世界的表现。
我相信这种约定在存储器行业中是相当标准的（每引脚比特率）。
BT
顺便说一句，
从我之前发布的帖子中可以看出，你不喜欢我说的话......我从初学者那里说“每一点”。
如果这不是更明显，我道歉



以下为原文

值得澄清的是，它是每个数据引脚的比特率，因为它们是移动数据中唯一涉及的引脚。
其余的（地址，控制）是控制接口的开销。



以下为原文

It may be worth clarifying that it is bitrate per data pin, since those are the only pins involved in moving data. The rest (address, control) are overhead to control the interface.

我们偏离了原来简单的一行问题。
但回到我原来的问题，
“内存控制器/ ddr（1 2或3）连续带宽有多大”
为了澄清，我会稍微重申一下。
“斯巴达6有一个专用的内存控制器。使用最快的斯巴达6和控制器支持的最快的DDR3内存，Xilinx可以预测连续的读写性能。 
一个澄清事物的假设例子。
如果我在斯巴达6中有一个连续的数据发生器，比如128位宽，200 MHz。
该数据发生器无法停止，必须在200 MHz下自由运行。
这些数据是否可以通过斯巴达6内的内存控制器不断写入DDR 3，控制器是否有足够的缓冲来处理控制器正在执行它的保持时间？
“



以下为原文

We have deviated a long way from the original simple one line question.
 
but to go back to my original question,
 
"Just how big is the memory controller / ddr ( 1 2 or 3 ) continuous bandwidth"
 
To clarify, I'll restate it slightly.
 
" the spartan 6 has a dedicated memory controller. Using the fastest spartan 6, and the fastest DDR3 memory the controller supports, does Xilinx have any numbers as to what continuous read or write performance can be expected .
 
A hypothetical example to clarify things.  If I have a continous data generator inside the spartan 6 of say 128 bits wide, at 200 MHz. This data generator can not be stopped, it must free run at the 200 MHz.  Can this data be constantly written to the DDR 3 by the memory controler inside the spartan 6, does the controler have sufficient buffering to take care of the times when the controler is performing it's house keeping ?  " 

我认为，试图建立对瓶颈和相关吞吐量的理解并不是对MCB实际应用的偏离......
例如，12.8Gbps（对于800Mbps的16位接口）相当于1.6GB / s的峰值带宽。
连续运行在200MHz的128位后端相当于16x 200MB / s或3.2GB / s。
显然，如果您无法停止数据，则无法做到这一点。
它也无法解决传输中的低效率或读取数据的问题（如果你不能停止，可能会交错，否则数据捕获最终会像逻辑分析器一样终止）。
BT



以下为原文

你好 
您似乎暗示Xilinx没有关于MCB可以应对的最大连续数据传输速率的信息。
如果是这样，你可以确认这一点，那么我很高兴我的原始问题得到了解答。



以下为原文

Hi
 
you seem to be implying that Xilinx have no information as to what the maximum continuous data transfer rate the MCB can cope with.
 
If that is so and you can confirm this, then I'm happy in that  my original question is answered.
 
 

您需要了解，带宽将取决于许多参数：您使用的内存类型，内存总线的宽度，实例化的MCB数量，数据访问模式是否随机等。
要回答关于最大带宽的假设性问题，请考虑以下问题：
1）您在x16 800Mbps模式下有4个MCB工作的芯片
2）你写入连续的内存块，没有任何随机访问
3）你只写入内存
那么最佳情况内存带宽（上限）将是4x16x800 = 51200Mbps = 6400兆字节/秒。
好？



以下为原文

You need to understand, that the bandwidth will depend on many parameters: what kind of memory you use, how wide is the memory bus is, how many MCBs you have instantiated, whether your data access pattern is random or not, etc.
 
To answer your hypothetical question about maximum bandwidth, consider the following:
1) You have a chip with 4 MCBs working in x16 800Mbps mode
2) You write to contiguous blocks of memory, no random access whatsoever
3) You only write to memory
 
Then the best case memory bandwidth(upper bound) will be  4x16x800=51200Mbps = 6400 Megabytes per second.
 
OK?

谢谢伊万，
那是我追求的数量和界限，
一个非常好的答案，



以下为原文

thank you Ivan,
 
that's the number and bounds I am after, 
 
A very good answer,
 
 

对于任何有答案的人来说，这是一个相关的问题。
根据UG388，您需要为MCB提供2倍内存总线频率的时钟，即800 MHz时钟以获得400 MHz总线（每个引脚上800 Mb / s）。在第80页，建议这是
时钟由一个主PLL驱动，然后通过BUFPLL_MCB（不改变频率），最后从那里进入MIG包装器核心。
所有这一切中唯一的问题是根据电气规范文件DS162，PLL不能超过375 MHz，将存储器总线限制在187.5 MHz。
时钟向导CoreGen似乎同意这个评估，那就是你是否将这些线输出到BUFG中。
谁知道那里有什么故事？



以下为原文

Here's a related question for anyone who's got an answer.  According to UG388, you need to provide the MCB with a clock at 2x the memory bus frequency, i.e. an 800 MHz clock to get a 400 MHz bus (800 Mb/s on each pin.)  On page 80, the recommendation is that this clock be driven from one of the main PLLs, then through a BUFPLL_MCB (which doesn't change the frequency) and finally from there into the MIG wrapper core.
 
The only problem in all of this is that according to electrical specs document DS162 the PLL is unable to exceed 375 MHz, limiting the memory bus to 187.5 MHz.  The Clocking Wizard CoreGen seems to agree with this assessment, and that's whether or not you output those lines into a BUFG.
 
Anyone know what the story is there?

您是否正在查看DS162中的36个，其中显示了带有BUFGMUX的PLL的375？
我想你应该看下一页列出Foutmax和BUFPLL（我认为我们需要BUFPLL_MCB）。
不幸的是，这还没有规范，但人们希望以足够的支持率运行MCB就足够了。
也许时钟向导使用唯一可用的号码，但会针对此案例进行更新。



以下为原文

Are you looking at 36 of the DS162 which shows 375 for the PLL with the BUFGMUX?  I think you should be looking at the next page which lists the Foutmax with the BUFPLL (I think we need BUFPLL_MCB).  Unfortunately this doesn't have a spec yet, but one would hope that it would be sufficient to run the MCB at its supported rate.  Perhaps the clocking wizard is using the only available number but will be updated for this case.

拾起并希望继续讨论，我发现-3，-3N，-2，-1L设备的频率为1080 1050 950 500，这说明1l无法运行400 MHz DDR。
（表51，第56页）。
参考最初的问题：
假设单芯片DDR3通过16Bit @ 400MHz x 2连接到MCB，并且平衡读取的最大效率为40％ - 写入 -  10％开销：这应该是大约650 MBps的连续数据传输。
我现在的问题是，如果最好使用4端口（2W + 2W）接口或更好的双端口（1R + 1W）和128位并手动管理访问而不是添加4个进程并让它们通过循环来管理
？



以下为原文

Picking up and hopefully continuing that discussion, I found the frequencies  1080 1050 950 500  for the -3, -3N, -2, -1L devices, which clarifies that the 1l cannot run a 400 MHz DDR. (Table 51, pg 56).
 
Referring to the initial question:
 
Assuming a one-chip DDR3 attached to the MCB by 16Bit @ 400MHz x 2 and 40% maximum efficiency for balanced read an write - 10% overhead : This should by around 650 MBps continuous data transfer.
 
My question now is, if it is better to use a 4 port (2W + 2W) interface or better a dual port (1R + 1W) with 128 Bits and manage access manually rather than adding 4 processes and let them be managed by round robin ?