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我有8个Spartan 6 FPGA设计原型和一个外部DDR RAM。
我使用Multi-Port-Memory-Controller并选择bank 3进行外部DDR-RAM连接。 我的Spartan 6 FPGA是“xc6slx75t-2fgg676”。 这种类型的bank 3需要4个参考电压IO(引脚T6,引脚W5,引脚AC4,引脚M9)和20k的分压器,最高可达1.8V,与评估板示例一样。 这在我的6个原型中运行良好。 当我连接到FPGA上的参考电压IO时,其中2个变为不同的电阻值,因此RAM数据流不起作用。 我手动手动测试参考电压引脚以排除出售的问题。 在我的工作板上,我在参考电压电阻12k上测量(当电路板未使用时,没有电压)。 在两个不工作的板上,我测量10k。 我不明白为什么或问题在哪里? 电阻器是相同的。 我包括2个电阻,20k,1%到1.8V,中间抽头用于4个FPGA参考电压IO。 我希望有人可以帮助我吗? 以上来自于谷歌翻译 以下为原文 I have 8 prototypes of Spartan 6 FPGA designs with a external DDR RAM. I use the Multi-Port-Memory-Controller and choose bank 3 for external DDR-RAM connection. My Spartan 6 FPGA is "xc6slx75t-2fgg676". This type on bank 3 needs 4 reference voltage IOs (Pin T6, Pin W5, Pin AC4, Pin M9) with a 20k votage divider up to 1.8V, like the evaluation board example. This works fine on 6 of my prototypes. 2 of them becomes different resistor values when i connect to the reference-voltage-IOs on the FPGA and so the RAM data flow not work. I manually test the reference voltage pins manually to exclude a sold problem. On my working boards I measure (when the board is not in use, no voltage) on the reference-voltage-resistors 12k. On the two not working boards I measure 10k. I dont understand why or where is the problem ? The resistors are the same. I include 2 resistors with 20k,1% to 1.8V and the middle tap is for the 4 FPGA-reference-voltage-IOs. I hope anybody can help me ? |
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9个回答
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对于DDR2设计,VREF应为0.9V。
重要的是电压,而不是电阻值。 GND和1.8V之间串联的两个相同电阻应在两个电阻之间的中心抽头处产生0.9V(1.8V除以2)。 检查设计摘要引脚列表,验证VREF引脚的引脚分配。 验证您使用的引脚是否已指定为VREF。 - 鲍勃埃尔金德 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 以上来自于谷歌翻译 以下为原文 For DDR2 designs, VREF should be 0.9V. It is the voltage which is important, not the resistor values. Two identical resistors in series between GND and 1.8V should result in 0.9V (1.8V divided by 2) at the centre tap between the two resistors. Check your design summary pin list, to verify the pin assignments of the VREF pins. Verify that the pins you are using are designated for VREF. -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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假设你有20.0K到1.8V和20.0K到GND,那么就是10.0K
你会在任何一个电阻上读到什么(假设大阻抗进入 FPGA)如果1.8V直接短路接地。 测量阻抗 在良好的电路板上从1.8V到GND,而不是坏电路板。 也建议衡量 电压,因为直接短路意味着没有1.8V而低阻抗 但不是直接短路可能只是意味着安装不正确的组件。 - Gabor - Gabor 以上来自于谷歌翻译 以下为原文 Assuming you have 20.0K to 1.8V and 20.0K to GND, then 10.0K is exactly what you would read across either resistor (presuming large impedance into the FPGA) if 1.8V were directly shorted to ground. Measure the impedance from 1.8V to GND on a good board vs a bad board. Also as suggested measure the voltage, because a direct short would mean no 1.8V while a low impedance but not direct short may just mean an incorrectly installed component. -- Gabor -- Gabor |
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只是一个想法,我似乎记得一些芯片在银行中有多个Vref点,
你有没有将银行中的所有vref引脚连接到vref,而不是将它们用作IO? 以上来自于谷歌翻译 以下为原文 just a thought, I seem to remember some chiops have multiple Vref poins in a bank, have you connected all the vref pins in the bank to vref, and not used them as IO ? |
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我会使用电压参考或小型稳压器来代替DDR2 VREF而不是电阻分压器。
----------------------------是的,我这样做是为了谋生。 以上来自于谷歌翻译 以下为原文 I would use a voltage reference, or a small regulator, for DDR2 VREF instead of resistive dividers. ----------------------------Yes, I do this for a living. |
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一般来说这不正确。
Vref必须跟踪VDD电压轨。 如果你使用电阻分压器 - 没有问题。 使用一般用途的LDO,你的设计是不正确的。 对DDR使用电阻分压器或SPECIAL参考。 以上来自于谷歌翻译 以下为原文 In general this incorrect. Vref MUST track VDD rail. If you use resistro divider - there is NO problem. With using general purposes LDO you design is incorrect. Use resistors divider or SPECIAL reference for DDR. |
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在现实生活中,VREF参考应来自产生VTT(DDR2终端电源)的相同吸收/源控制器。
该调节器(有时)还将提供专用的VREF信号,大多数(可能是所有)存储器控制器和DDR2存储器设备都需要该信号。 如果用于VTT的稳压器不提供单独的VREF输出,则从稳压器VTT引脚到控制器VREF引脚和DRAM VREF引脚的开尔文连接走线就足够了。 以下是一个提供专用VREF输出的稳压器示例。 单卷数量约为0.75美元。 以下是不提供专用VREF输出的稳压器示例。 单卷数量约为0.24美元。 这是有多种方法来解决同一问题的应用程序之一。 就个人而言,我使用廉价的稳压器,使用VTT电源进行VREF(带开尔文连接)。 布线以使耦合噪声最小化,并在负载引脚处插入去耦帽。 - 鲍勃埃尔金德 签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。 阅读手册或用户指南。 你读过手册了吗? 你能找到手册吗?2。 搜索论坛(并搜索网页)以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题,开始新的主题!5。 学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息(请与网页,数据表链接).7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章,那么我一无所获。 以上来自于谷歌翻译 以下为原文 In real life, the VREF reference should be derived from the same sink/source regulator which generates VTT (the DDR2 termination supply). This regulator will (sometimes) also provide a dedicated VREF signal which most (perhaps all) memory controllers and DDR2 memory devices require. If the regulator you are using for VTT doesn't provide a separate VREF output, then a Kelvin-connected trace from the regulator VTT pin to the controller VREF pins and DRAM VREF pins will suffice. Here is an example of a regulator which provides a dedicated VREF output. About $0.75 in single-reel quantities. Here is an example of a regulator which does not provide a dedicated VREF output. About $0.24 in single-reel quantities. This is one of those applications where there are multiple ways to solve the same problem. Personally, I use the inexpensive regulator, using the VTT supply for VREF (with Kelvin connections). Route the traces to minimise coupling noise, and throw in a decoupling cap at the load pins. -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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在现实生活中,VREF参考应来自产生VTT(DDR2终端电源)的相同吸收/源控制器。
该调节器(有时)还将提供专用的VREF信号,大多数(可能是所有)存储器控制器和DDR2存储器设备都需要该信号。 如果用于VTT的稳压器不提供单独的VREF输出,则从稳压器VTT引脚到控制器VREF引脚和DRAM VREF引脚的开尔文连接走线就足够了。 以下是一个提供专用VREF输出的稳压器示例。 单卷数量约为0.75美元。 以下是不提供专用VREF输出的稳压器示例。 单卷数量约为0.24美元。 这是有多种方法来解决同一问题的应用程序之一。 就个人而言,我使用廉价的稳压器,使用VTT电源进行VREF(带开尔文连接)。 布线以使耦合噪声最小化,并在负载引脚处插入去耦帽。 - 鲍勃埃尔金德 以上来自于谷歌翻译 以下为原文 In real life, the VREF reference should be derived from the same sink/source regulator which generates VTT (the DDR2 termination supply). This regulator will (sometimes) also provide a dedicated VREF signal which most (perhaps all) memory controllers and DDR2 memory devices require. If the regulator you are using for VTT doesn't provide a separate VREF output, then a Kelvin-connected trace from the regulator VTT pin to the controller VREF pins and DRAM VREF pins will suffice. Here is an example of a regulator which provides a dedicated VREF output. About $0.75 in single-reel quantities. Here is an example of a regulator which does not provide a dedicated VREF output. About $0.24 in single-reel quantities. This is one of those applications where there are multiple ways to solve the same problem. Personally, I use the inexpensive regulator, using the VTT supply for VREF (with Kelvin connections). Route the traces to minimise coupling noise, and throw in a decoupling cap at the load pins. -- Bob Elkind |
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我讨厌打破这个爱情节,但阅读原版可能有意义
帖子。 特别: A)8个原型板中的6个工作正常。 B)两块不能正常工作的电路板在阻抗方面存在可测量的差异 在电阻分压器处。 这似乎暗示了某处的短路,很可能是从+ 1.8V到地面。 在我看来这不是一个设计缺陷。 更可能是焊接不好。 - Gabor - Gabor 以上来自于谷歌翻译 以下为原文 I hate to break up this love-fest, but it might make sense to read the original post. Specifically: A) 6 of the 8 prototype boards work fine. B) The two boards that don't work fine have a measurable difference in impedance at the resistor divider. This seems to suggest a short circuit somewhere, most likely from +1.8V to ground. It hardly seems to me that this is a design flaw. Much more likely bad soldering. -- Gabor -- Gabor |
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A)8个原型板中的6个工作正常。
根据原帖,我对此持怀疑态度。 它可能不成立 随着时间的推移/温度。 或者它可能就像书面一样。 自原来 帖子没有包含电压测量,对此持怀疑态度 dbau的分析 情况。 事实上,没有经过适当示波器验证的VREF电压 (和噪声)水平测量,任何VREF导致的结论 “RAM数据流不起作用”的问题为时过早。 简单地说,没有足够的信息。 你这里的帖子并不矛盾。 我只是说你只能回答问题, 并没有做出如此多的假设以至于偏离轨道。 如果你看看我的第一篇文章,建议 测量1.8V也意味着OP还没有完成他的所有功课。 我从来没有亲自过 使用Vref的电阻分压器的问题,只要我知道我正在附加它。 我碰到了 但是,使用来自组合Vtt电源和Vref发生器的Vref的问题。 问题确实存在 与Vref电压产生的方式无关,它与我没有做的事实有关 了解具有SSTL输出但没有SSTL输入的银行不仅不需要Vref, 但是没有保留Vref引脚,所以他们都得到了默认的未使用的IOB动作 - 在我的情况下 将“弱势”拉向Vcco。 在这种情况下,Vref发生器不是为了下拉而设计的 当接近Vcco时,Vref引脚上的电压。 实际上是一个电阻分压器 在这种情况下更好。 B)两块不能正常工作的电路板在电阻分压器处的阻抗存在可测量的差异。 我不会依赖于“阻抗测量”到轨道或GND 一个无动力的董事会。 被动和主动的路径太多了 1.8V和GND之间的元件使其成为......的可靠指标 任何东西。 这似乎暗示了某处的短路,很可能是从+ 1.8V到地面。 对此的字面解读可以预测一阵烟雾,或者 一些东西。 如果一些不太明显的短片正在发挥作用,那就是“范围验证” VREF水平和'噪音'应检测到它。 多年来我一直有很多电路板,电源轨上没有短路,没有“烟雾”。 根据我的经验,电源通常通过短路事件来实现,因为它们是 旨在做到这一点。 如果短路的源可以处理所施加的电流(通常是这样) 焊接短路的情况)然后没有释放魔法烟雾。 我同意你的需要 测量电压,而不仅仅是电阻,以确定RAM“不工作”的原因。 事实上,我认为没有1.8V供电可能是导致非工作RAM的原因 Vref电源的问题,以及没有提到电压的事实 原始帖子意味着他甚至可能甚至没有测量供应本身。 所以给出了信息 由于缺少或供应短缺,他的董事会似乎更有可能无法工作 电压比因为他的电阻分压器没有正确产生1/2 Vcco。 无论如何,我们现在可能已经吓坏了他。 幸运的是,他很久以来 发现了实际问题并继续...... - Gabor - Gabor 以上来自于谷歌翻译 以下为原文 A) 6 of the 8 prototype boards work fine.Based on the original post, I'm skeptical of this. It might not hold up over time/temp. Or it might be just as written. Since the original post didn't include a voltage measurement, it's fair to be skeptical of dbau's analysis of the situation. In fact, without a proper oscilloscope-verified VREF voltage (and noise) level measurement, any conclusion that VREF is the cause of the "RAM data flow not work" problem is premature. Simply put, there's not enough information. You're not contradicting my post here. I'm just saying you can only answer the question as asked, and not make so many assumptions as to go off track. If you look at my first post, the suggestion to measure 1.8V also implied that the OP didn't do all his homework yet. I've never personally had a problem using a resistor divider for Vref, as long as I know what I'm attaching it to. I did run into problems using Vref from a combo Vtt supply and Vref generator, though. The problem really had nothing to do with the way the Vref voltage was generated, it had to do with the fact that I didn't understand that banks with SSTL outputs but without SSTL inputs not only did not need Vref, but did not reserve the Vref pins so they all got the default unused IOB action - in my case pulled "weakly" to Vcco. In this case the Vref generator was not designed to pull down, so the voltage on the Vref pins when nearly to Vcco. A resistor divider would have actually been better in this case. B) The two boards that don't work fine have a measurable difference in impedance at the resistor divider.I wouldn't rely on "impedance measurements" to the rails or GND for an unpowered board. There are too many paths through passive and active components between 1.8V and GND to make this a reliable indicator of... anything. This seems to suggest a short circuit somewhere, most likely from +1.8V to ground.A literal reading of this would predict a puff of smoke, or something. If some less obvious short is in play, a 'scope verification of VREF level and 'noise' should detect it. I've had lots of boards over the years with dead shorts on the power rails and no "puff of smoke." In my experience the power supplies usually live through shorting events because they are designed to do just that. If the source of the short can handle the applied current (as is often the case with solder shorts) then there is no magic smoke released. And I agree you need to measure voltages, not just resistance, to determine the cause of the RAM "not working." In fact I would argue that no 1.8V supply is as likely a cause for non-working RAM as a problem with the Vref supply, and the fact that there were no voltages mentioned in the original post means he likely didn't even measure the supply itself. So given the information at hand it seemed more likely that his boards don't work due to missing or shorted supply voltages than because his resistor divider was not properly generating 1/2 Vcco. In any case we've probably scared him off by now. With any luck he's long since found the actual problem and moved on... -- Gabor -- Gabor |
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