请问有没有办法使用当前的设计工具为SPARTAN II开发代码？

T，
较旧的工具保存在“经典”区域。
http://www.xilinx.com/webpack/classics/wpclassic/
Austin Lesea主要工程师Xilinx San Jose



以下为原文

t,
 

Older tools are kept in the "classics" area.
 
http://www.xilinx.com/webpack/classics/wpclassic/
Austin Lesea
Principal Engineer
Xilinx San Jose

对你的代码进行简短的评论（今天下午我的模拟很长！）：1。
“位置关联”的组件端口映射不如使用“命名关联”.2。
很高兴看到你已经为你的流程命名了。
对于'LUT_addr_proc'，'sum_high_out_proc'，'fifo_data_in_proc'，您的过程敏感性列表是错误的。
由于它们是组合的，它们不应包括'clk'或其他未实际使用的信号，因为这可能导致模拟/合成不匹配。
在您的流程中粘贴多个空行会降低可读性。
如果工具支持，则应使用包IEEE.numeric_std而不是IEEE.std_logic_arith（遗留综合工具可能不支持）。
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

A short critique on your code (my simulation is a long one this afternoon!):
1. Component port maps by "positional association" are less robust than using "named association".
2. Glad to see you have named your processes.
3. Your process sensitivity lists are WRONG for 'LUT_addr_proc', 'sum_high_out_proc', 'fifo_data_in_proc'. As they are combinational, they should not include 'clk', or other signals not actually used, as this may cause simulation/synthesis mismatches.
4. Sticking multiple blank lines in your processes detracts from readability.
5. Package IEEE.numeric_std should be used rather than IEEE.std_logic_arith if the tools support it (legacy synthesis tools might not).
------------------------------------------
"If it don't work in simulation, it won't work on the board."

此外，如果从“经典”工具页面中不清楚，版本10.1.03i是最后一个版本
支持Spartan II。
请注意，这些部件是寿命终结，因此您不想使用它们
对于新设计。
-  Gabor
-  Gabor



以下为原文

Also if it wasn't clear from the "classics" tools page, version 10.1.03i is the very last version
to support Spartan II.  And note that these parts are end of life, so you don't want to use them
for new designs.
 
-- Gabor
-- Gabor