请问这个分开的代码PSoC4有什么特点？

是的，PSoC4会来的。塞浦路斯对它的特性保持了一些犹豫，但我怀疑它的核心将是一个手臂M0来保持它的便宜。有一些视频比较了8051内核和ARM M0，而不是皮质M3，我怀疑这背后的原因。哪种模拟和数字硬件模块即将到来？让我猜猜：美国太空站的概念和结构是成功的，所以“永远不要改变获胜的队伍”。
鲍勃



     以下为原文
  Yes, a PSoC4 will come. Cypress keeps a bit qiuet about its features, but I suspect that the core will be an ARM M0 to keep it cheap. There are some videos which compare the 8051 core to ARM M0 and not to Cortex M3, I suspect a reason behind that. Which analog and digital hardware modules are to come? Let me guess: the concept and the structure of USBs is successful, so "never change a winning team".
    Bob

不是USB！！！！当然是UDB！
鲍勃



     以下为原文
  Not USB!!! UDB of course!
     
    Bob

…还有一个：一个近一年的线索，讨论同一个主题。现在我们可以想象，至少需要一年，直到有PSOC4的工程样本（微笑）。
HTTP://www. CyPress？COM/？APP =论坛和RID＝57268
鲍勃



     以下为原文
  ... and one more: here is a link to a nearly one-year old thread discussing the very same theme. Now we can imagine that it will take at least anothere year until there are engeneering samples of a PSoC4 (Smile)
    http://www.cypress.com/?app=forum&rID=57268
     
    Bob

我们已经对PSoC4特别关注了一年了。一个PSoC今天的视频暗示我们将得到一个CordX-M0 PSoC，所以我们推测它将是传奇的PSoC4。不过，目前还没有官方消息。



     以下为原文
  We have been especulating about  PSOC4 for about a year already. A PSOC today video hinted that we were going to get a Cortex-m0 PSOC so we asumed it would be the legendary PSOC4. Still, there are no official news about it tho.

投机已经结束：
San若泽，Calif.，2013年3月20日-赛普拉斯半导体公司（NASDAQ:CY）今天推出了PSoC®4可编程系统片上架构，它结合了赛普拉斯的最好的PSoC模拟和数字织物和业界领先的CopSunch®电容触摸技术与ARM®的POWER效率皮质μ-M0核。
在www. CyPress .COM/GO/PSoC4中阅读更多信息
谢谢！
吉姆



     以下为原文
   Speculation is over:
    SAN JOSE, Calif., March 20, 2013 – Cypress Semiconductor Corp. (NASDAQ: CY) today unveiled the PSoC® 4 programmable system-on-chip architecture, which combines Cypress’s best-in-class PSoC analog and digital fabric and industry-leading CapSense® capacitive touch technology with ARM®’s power-efficient Cortex™-M0 core.
    Read more at www.cypress.com/go/PSoC4
    thanks!
    Jim

我刚刚阅读了关于www.
这是一个CordX-M0。它是低功耗的。



     以下为原文
  I've just read the news on www.embedded.com
    it is a Cortex-M0. and it comes with low power consumtion.

感谢让社区知道PSoC 4将是真实的。当我看你提到的网站时，数据明显缺乏。
这里是什么（类似）
12位模数转换器
运算放大器，比较器，IDAC，精密电压基准。
--------
“创新”措辞
“停止模式只消耗20 NA，同时仍保持唤醒的能力，由极低功率保持睡眠模式补充，只吸引150 NA而不干扰SRAM数据”
？在不干扰SRAM数据的情况下？猜想它意味着在充分保留SRAM内容的同时
----------
从建筑简报。
“大多数可重新配置的ARM CORTEX-M0”OOPS - CyPress拥有一个架构许可证来重新配置核心吗？
在等待数天之后，是否还有更多的数据要消化，我有点失望什么（不）传达关于PSoC 4。
失踪：
-包裹？
PSoC 4是否升级到PSoC 3？- CPU指示“是”8位-gt；32位，ADC指示20位-gt；12位；
-记忆？32 K/8K？64K/8K？128K/12K与市场上其他M0设备一样？
-马克斯频率？PSoC不是关于高频的，他承认，在PSoC 4的计算性能中可以使用哪些算法仍然是非常有趣的。
-低功耗模式下的电流消耗是重要的，然而，有时需要激活设备-激活模式下的消耗？
-是否有一个用于创建者2.2的开关来完全激活PSoC 4？还是我们在等待创造者2.3（3）？
-视频包括一个UBB-FS块（39秒和1∶15分钟），架构概要没有-是什么？
塞浦路斯宣布一个新的设备，新闻发布的信息很少，这是不寻常的。关于PSoC 4的谣言已经在这个论坛上逗留了一年多，一定有一些类似于PrL的东西。数据表！
请张贴！



     以下为原文
   Thanks for letting the community know that PSoC 4 will be real. When I looked at the website you mentioned, there was an obvious lack of data.
     Here is what I found (and like)
     12-bit ADC
     Op-Amps, Comparators, IDACs, precision voltage reference.
     --------
     "Innovative" wording
     " stop mode consuming only 20 nA while still retaining its ability to wake up, complemented by an extremely low-power retention sleep mode that draws only 150 nA without disturbing SRAM data"
     ? without disturbing SRAM data ? Guess it means while fully retaining SRAM content
     ---------
     From the     architecture brief.
     "Most Reconfigurable ARM Cortex-M0" Oops - Does Cypress own an architecture license to reconfigure the core?
     After waiting a few days whether there is going to be more data to digest, I am somewhat disappointed what is (not) communicated about PSoC 4
     Missing:
     - packages?
     - is the PSoC 4 an upgrade to PSoC 3? - The CPU indicates yes 8-bit -> 32-bit, The ADC indicates otherwise 20-bit -> 12-bit?
     - memory? 32k/8k ? 64k/8k? 128K/12k like other M0 devices on the market?
     - Max frequency? PSoC is not about high frequency, acknowledge that, it is still very interesting what algorithms can be used within the computing performance of the PSoC 4
     - current consumption in low power modes are important, however, sometimes the device needs to be activated - consumption in active mode?
     - is there a switch for Creator 2.2 to fully activate PSoC 4? - or are we waiting for Creator 2.3 (3.0)?
     - the video included a USB-FS block (39sec and 1:15min), the architecture brief does not - what is it?
     It is unusual for Cypress to announce a new device with so little information accompanying the press release. Rumors about PSoC 4 have been lingering in this forum for more than a year, there must be something like a prel. data sheet!
     Please post it!

您提到的降低ADC分辨率来自于PSoC4附带一个SAR ADC，它运行在1MSPS（像PSoC5LP）。PSCO3没有DelSig ADClike。但是，正如我们在另一个线程中所学到的，我们可以用可用的组件和UDB构建一个线程。或者你只是使用过采样…



     以下为原文
  The reduced ADC resolution you mentioned comes from the fact that the PSoC4 comes with a SAR ADC, which runs at 1MSpS (like the PSoC5LP). There is just no DelSig-ADC like the PSoC3 has. But as we learned in another thread here, one could build one with theavailable components and the UDB. Or you just use oversampling...