请帮助我解决Block RAM问题？

您发布的文件说它是使用Altera megawizard生成的。
您
需要使用Xilinx的“核心生成器”生成FIFO。
这将允许你
生成一个正常工作的FIFO，并根据宽度，深度，内存对其进行自定义
用法（块与分布式），时钟等。其中一种变体可能是
与您要替换的Altera FIFO非常相似。
然后只需放一个包装纸
使端口与原始Altera实现相匹配的核心。
如果你
使用ISE Navigator GUI，转到：
项目 - >新来源......
选择“IP（CORE Generator＆amp; Architecture Wizard）
为核心分配模块名称
然后浏览到Memories＆amp;
存储元素 - > FIFO
并选择FIFO Generator。
如果您需要有关FIFO核心定制的帮助，只需打开即可
自定义程序窗口中的数据表。
HTH，
的Gabor
-  Gabor



以下为原文

The file you posted says it was generated using the Altera megawizard.  You
need to generate a FIFO using "core generator" for Xilinx.  This will allow you
to generate a FIFO that works properly and customize it for width, depth, memory
usage (block vs. distributed), clocking, etc.  One of the variants is likely to be
very similar to the Altera FIFO you are replacing.  Then just put a wrapper around
the core to make the ports match your original Altera implementation.  If you
use the ISE Navigator GUI, go to:
Project --> New Source...
Select "IP (CORE Generator & Architecture Wizard)
Assign a module name for the core
Then browse to Memories & Storage Elements --> FIFOs
and select FIFO Generator.
If you need help with customization of the FIFO core, just open the
data sheet from the customizer window.
 
HTH,
Gabor
-- Gabor

嗨Gabor，
我确实使用Core Generator来生成altdp_fifo3.xco文件。
因此，CoreGen设置存在问题。
当我合成时，没有错误。
提到的错误仅在我使用bitgen生成比特流文件时出现。
问题是如何绕过CoreGen GUI设置来解决问题。
为了帮助识别问题，我还附上了来自ipcore_dir目录的CoreGen生成的altdp_fifo3.v。
我使用的是ISE版本12.2（nt），应用程序版本：M.63C。
谢谢，
胜利者
altdp_fifo3.v 5 KB



以下为原文

Hi Gabor,
 
I did use Core Generator to generate altdp_fifo3.xco file. Hence it is a problem with CoreGen settings. When I synthesize, there were no errors. The errors mentioned appear only when I generate the bitstream file using bitgen. The question is how to get around the CoreGen GUI settings to  solve the problem.
 
To help identifying the issues, I am enclosing also altdp_fifo3.v generated by the CoreGen from the ipcore_dir directory.
 
I am using ISE Release Version 12.2(nt), Application version: M.63C.
 
Thanks,
Victor
            altdp_fifo3.v ‏5 KB

vramamoorthy写道：
嗨Gabor，
我确实使用Core Generator来生成altdp_fifo3.xco文件。
因此，CoreGen设置存在问题。
当我合成时，没有错误。
提到的错误仅在我使用bitgen生成比特流文件时出现。
问题是如何绕过CoreGen GUI设置来解决问题。
为了帮助识别问题，我还附上了来自ipcore_dir目录的CoreGen生成的altdp_fifo3.v。
我使用的是ISE版本12.2（nt），应用程序版本：M.63C。
谢谢，
胜利者
不要使用核心发生器。
如果它们是合理的，则推断Verilog的记忆（读写侧纵横比相同）。
否则，RTFM看看如何直接实例化它们。
你会好多了。
----------------------------是的，我这样做是为了谋生。



以下为原文

 

vramamoorthy wrote:
Hi Gabor,
 
I did use Core Generator to generate altdp_fifo3.xco file. Hence it is a problem with CoreGen settings. When I synthesize, there were no errors. The errors mentioned appear only when I generate the bitstream file using bitgen. The question is how to get around the CoreGen GUI settings to  solve the problem.
 
To help identifying the issues, I am enclosing also altdp_fifo3.v generated by the CoreGen from the ipcore_dir directory.
 
I am using ISE Release Version 12.2(nt), Application version: M.63C.
 
Thanks,
Victor

 
Don't use the core generator.
 
Infer the memories from your Verilog if they are reasonable (read and write side aspect ratios are the same).
Otherwise, RTFM to see how to instantiate them directly.
 
You'll be a lot better off.
----------------------------Yes, I do this for a living.

bassman59写道：
--------------------------------------------------
---------------------------------------
不要使用核心发生器。
如果它们是合理的，则推断Verilog的记忆（读写侧纵横比相同）。
否则，RTFM看看如何直接实例化它们。
你会好多了。
--------------------------------------------------
--------------------------------------
请问解释什么是RTFM？
因为我很困惑，请帮我详细说明。
谢谢，
胜利者



以下为原文

bassman59 wrote:
-----------------------------------------------------------------------------------------
Don't use the core generator.
 
Infer the memories from your Verilog if they are reasonable (read and write side aspect ratios are the same).
Otherwise, RTFM to see how to instantiate them directly.
 
You'll be a lot better off.
----------------------------------------------------------------------------------------
 
Could please explain what is RTFM?  Please help me out with details as I am confused.
 
Thanks,
Victor

vramamoorthy写道：
请问解释什么是RTFM？
因为我很困惑，请帮我详细说明。
----------------------------是的，我这样做是为了谋生。



以下为原文

 

vramamoorthy wrote:
 
Could please explain what is RTFM?  Please help me out with details as I am confused.

 
----------------------------Yes, I do this for a living.

我之前说的是使用核心生成器生成_FIFO_。
你做的是使用核心生成器生成_Block RAM Memory_。
贝斯曼59所说的是“不要用核心发电机来制造记忆”，这就是
好建议。
如果您不希望核心生成器完成FIFO的所有逻辑，
那么你最好的选择是使用XST中提供的模板推断内存
手册。
有一章关于推断块存储器。
总而言之，我使用核心生成器_FIFO_没有问题
核心，所以显而易见的是看你是否能在项目中达到一个水平
层次结构并替换Altera Megawizard FIFO的所有遗留物
使用CoreGen FIFO。
-  Gabor
-  Gabor



以下为原文

What I said originally was to generate a _FIFO_ using the core generator.
 
What you did was to generate a _Block RAM Memory_ using the core generator.
 
What bassman59 says is "don't use core generator to make memories" and this is
good advice.  If you don't want the core generator to make all of the logic of your FIFO,
then your best bet is to infer the memory using the templates provided in the XST
manual.  There is a chapter on inferring block memory.
 
All in all though, I have had no problem using the core generator _FIFO_
cores, so the obvious thing is to see if you can go up a level in your project
hierarchy and replace all of the remains of the Altera Megawizard FIFO
using a CoreGen FIFO.
 
-- Gabor
-- Gabor

>请解释什么是RTFM？
因为我很困惑，请帮我详细说明。
这意味着阅读精细手册（或适当的数据表或用户指南）。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

> Could please explain what is RTFM?  Please help me out with details as I am confused.
 
It means Read The Fine Manual  (or datasheet or user guide as appropriate).
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

>错误：PhysDesignRules：1162  - 无效配置（错误的引脚连接和/或模式）打开
>块::
>。
该块配置为使用DIPAO，但此引脚未连接
我不认为这是原始错误消息的剪切和粘贴，DIPAO应该是DIAPA0，DIPA或DOPA。
无论哪个是正确的名称，如果您不使用Block RAM中的奇偶校验位，则将DIPA（和DOPA）输入连接到逻辑0或1。
>警告：PhysDesignRules：1098  -  BlockRAM没有数据输入。
comp的写使能引脚WEA0
> dp_fifo3 / altdp_fifo3_int / BU2 / U0 / blk_mem_generator / valid.cstr / ramloop [2] .ram.r / s3a_noinit.ram / dpram.ram
>有一个有效信号，但没有连接数据输入引脚。
无效数据可能会写入BlockRAM
此消息表示您已将有效信号连接到端口A上的写入使能，但未连接数据输入引脚（DIA）。
这可能是由于在合成或地图阶段期间网被修剪。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

> Error: PhysDesignRules: 1162 - Invalid configuration (incorrect pin connections and/or modes) on
> block: :
> . The block is configured to use DIPAO, but this pin is not connected
 
I don't think that this is a cut-and-paste of the original error message and DIPAO should be either DIAPA0, DIPA or DOPA.  Regardless of which one is the correct name, if you are not using the parity bits in the Block RAM then connect the DIPA (and DOPA) inputs to either logic 0 or 1.
 
> Warning: PhysDesignRules: 1098 - BlockRAM has no data input. The Write Enable pin WEA0 of comp
> dp_fifo3/altdp_fifo3_int/BU2/U0/blk_mem_generator/valid.cstr/ramloop[2].ram.r/s3a_noinit.ram/dpram.ram
> has an active signal but no data input pins are connected. Invalid data may be written to BlockRAM
 
This message indicates that you have an active signal connected to the Write Enable on Port A, but that Data Input pins (DIA) are not connected.  This may be due to nets being trimmed during the synthesis or map phase.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

嗨mcgett，
我附上了整个编译会话报告。
它确实说DIPA0！
我还使用CoreGen在我的代码中生成其他Blockrams。
他们似乎都工作。
但是当我尝试使用32 x 2048尺寸的bram时它会出现问题。
我不知道为什么会这样。
在以前版本的ISE中，它完成了所有这些，没有任何错误。
出了点问题 -  RTFM在这里不起作用 - 我花了两个小时倾注ug331.pdf的“Using Block RAM”一章。
请帮忙！
不要强迫我回阿尔特拉！
它在那里工作得很好!!!
谢谢，
胜利者
Xilinx error.rtf 25 KB



以下为原文

Hi mcgett,
 
I am attaching the entire compile session report. It does say DIPA0!
 
I also use CoreGen to generate other Blockrams in my code. They all seem to work. But it has problems when I try to use 32 x 2048 size bram. I don't know why it does it. In the previous version of ISE, it did all these without any errors.
 
Something is wrong - RTFM does not work here - I spent two hours pouring over the "Using Block RAM" chapter of ug331.pdf.
 
Please help! Don't force me to go back Altera!!  It works fine there!!!
 
Thanks,
Victor 
            Xilinx error.rtf ‏25 KB

您应该在“工具”菜单下的原理图查看器中浏览此BRAM，以查看与它的连接是否符合您的预期。
-R
--------------------------------------------------
--------------------------不要忘记回复，不要接受作为解决方案-----------
--------------------------------------------------
---------------



以下为原文

You should explore this BRAM in the schematic viewer under the Tools menu to see if the connections to it are what you expect.
 
-R
----------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution
----------------------------------------------------------------------------

roym写道：
您应该在“工具”菜单下的原理图查看器中浏览此BRAM，以查看与它的连接是否符合您的预期。
-R
做RTFM并查看日志输出，我认为CoreGen创建了一个带有奇偶校验位的bram。
我想要的是没有奇偶校验位的简单bram。
（1）如何欺骗CoreGen以便它不会创建奇偶校验位？
我想要一个大小为32 x 2048的bram，没有奇偶校验位需要担心。
（2）如果（1）不可能，我应该怎么处理奇偶校验位？
我可以将它们全部设置为零或一个吗？
（3）如果我必须使用verilog推断实例化，我该怎么做？
谢谢，
胜利者



以下为原文

roym wrote:
You should explore this BRAM in the schematic viewer under the Tools menu to see if the connections to it are what you expect.
 
-R

 
Doing RTFM and looking at the log output, I think that CoreGen has created a bram with parity bits. What I want is simple bram without parity bits.
 
(1) How do I trick the CoreGen so that it does not create parity bits? I want a bram for the size of 32 x 2048 having no parity bits to worry about.
 
(2) If (1) is not possible, what should I do with parity bits?  Can I set them all to zero or one?
 
(3) If I have to infer instantiation with verilog, how do I do that?
 
Thanks,
 
Victor
 
 

我认为CoreGen有
用奇偶校验位创建了一个bram。
我想要的是简单的bram没有
奇偶校验位。
BRAM原语是（本机的）18位宽。
文档将18位中的2个标记为奇偶校验位，但它们在各方面都与其他BRAM位无法区分。
您可以使用它们来存储奇偶校验，但这完全取决于您。
（1）如何欺骗CoreGen以使其不创建奇偶校验
位？
我想要一个32 x 2048大小的bram，没有奇偶校验位
担心。
Coregen（FIFO向导）应该为您做到这一点。
（2）如果（1）不可能，我应该怎么处理奇偶校验位？
我可以将它们全部设置为零或一个吗？
（1）是可能的，问题没有实际意义。
（3）如果我必须使用verilog推断实例化，我该怎么做？
在ISE中，在设计层次结构窗格中，选择向导生成的FIFO。
在“进程”窗格（它出现在我的ISE设置的左下角）中，双击“查看HDL实例化模板”。这将显示一个源代码模板，用于将您的设计粘贴到您的设计中（如您所愿）
不要忘记给每个实例一个唯一的实例名称）。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

I think that CoreGen has created a bram with parity bits. What I want is simple bram without parity bits.

The BRAM primitive is (native) 18 bits wide.  The documentation labels 2 of the 18 bits as parity bits, but they are indistinguishable from the other BRAM bits in every way.  You can use them for storing parity, but that is strictly up to you.

(1) How do I trick the CoreGen so that it does not create parity bits? I want a bram for the size of 32 x 2048 having no parity bits to worry about.

Coregen (FIFO wizard) should do that for you.

(2) If (1) is not possible, what should I do with parity bits?  Can I set them all to zero or one?

(1) is possible, question is moot.

(3) If I have to infer instantiation with verilog, how do I do that?

In ISE, in the design hierarchy pane, select the FIFO which the wizard has generated.  In the 'processes' pane (it appears in the bottom left corner in my ISE setup), double-click on 'View HDL Instantiation Template".  This brings up a source code template for pasting into your design as many instances as you like (don't forget to give each instance a unique instance name).
 

 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

嗨鲍勃，
当只有数据进入而数据在另一端出来时，我真的在寻找标准的FIFO。
我想要的几乎就像双端口存储器，输入地址和输出地址不同。
换句话说，我应该可以在任何地方写入并从任何地址获取数据。当我写入数据时，我顺序递增地址，就像循环缓冲区一样。
当我读出时，输出数据地址几乎可以在RAM内。
我不想要奇偶校验位的麻烦。
可能吗？
谢谢你的支持。
我非常感谢你的详细解答。
谢谢，
胜利者



以下为原文

Hi Bob,
 
I am really looking for a standard FIFO when there is only data going in and data coming out in the other end. What I want is almost like a dual port memory where the input address and output address are different. In other words, I should be able to write in anywhere and get the data out from any address, When I write the data in, I sequentially increment the address almost like a circular buffer with wrap around. When I read out, the out data address can be almost anything within the RAM. I don't want the hassle of parity bits.
 
Is it possible?
 
Thanks for the handholding. I really appreciate your detailed answer.
 
Thanks,
Victor

你真的运行过FIFO发生器吗？
如果没有，那么请立即停止并运行FIFO生成器，然后再提出任何问题。
当只有数据进入而数据在另一端出来时，我真的在寻找标准的FIFO。
到目前为止听起来很正常......
我想要的几乎就像双端口存储器，输入地址和输出地址不同。
还是很正常......
换句话说，我应该可以在任何地方写入并从任何地址获取数据
你开始担心我了。
你想描述随机访问吗？
如果是这样，这不是FIFO，它是双端口RAM。
当我写入数据时，我按顺序递增地址...
地址指针在向导生成的FIFO内部。
我担心你可能已经阅读了精美的手册，但你不了解基础知识。
......几乎像一个带环绕的圆形缓冲区。
您是否需要在写入时进行环绕，因此您可以覆盖尚未读取的FIFO条目？
（超限运行）
或者您是否需要在读取时进行环绕，因此您可以读取已经获取的FIFO条目？
（下运行）
说真的，您认为FIFO发生器缺少什么？
当我读出时，输出数据地址几乎可以在RAM内
这听起来有点随意......我真的希望我们在这里遇到语言困难，而且没有比那更邪恶的了。
我不想要奇偶校验位的麻烦。
这听起来像你不理解我以前的帖子（我特别介绍了奇偶校验位的主题）。
请向我们解释您认为这意味着什么：
我认为CoreGen有
用奇偶校验位创建了一个bram。
我想要的是简单的bram没有
奇偶校验位。
BRAM原语是（本机的）18位宽。
文档
将18位中的2个标记为奇偶校验位，但它们无法区分
从各个方面的其他BRAM位。
您可以使用它们进行存储
平价，但这完全取决于你。
（1）如何欺骗CoreGen以使其不创建奇偶校验
位？
我想要一个32 x 2048大小的bram，没有奇偶校验位
担心。
Coregen（FIFO向导）应该为您做到这一点。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Have you actually run the FIFO generator?  If not, then please STOP NOW and run the FIFO generator before you ask any more questions.

I am really looking for a standard FIFO when there is only data going in and data coming out in the other end.

Sounds pretty normal so far...

What I want is almost like a dual port memory where the input address and output address are different.

Still pretty normal...

In other words, I should be able to write in anywhere and get the data out from any address

You're starting to worry me.  Are you trying to describe random access?  If so, this isn't a FIFO, it's a dual port RAM.

When I write the data in, I sequentially increment the address...

The address pointers are internal to the FIFO generated by the wizard.  I'm worried you may have read the fine manual, but you don't understand the basics.

... almost like a circular buffer with wrap around.

Do you require wraparound on write, so you can over-write FIFO entries which haven't been read? (over-run)
Or do you require wraparound on read, so you can read FIFO entries which have already been fetched? (under-run)
 
Seriously, what do you think you are missing from the FIFO generator?

When I read out, the out data address can be almost anything within the RAM

That sounds a bit random...  I really hope we're having language difficulties here, and nothing more sinister than that.

I don't want the hassle of parity bits.

This sounds like you did not comprehend my previous post (I specifically covered the subject of parity bits).  Please explain to us what you think this means:

I think that CoreGen has created a bram with parity bits. What I want is simple bram without parity bits.

The BRAM primitive is (native) 18 bits wide.  The documentation labels 2 of the 18 bits as parity bits, but they are indistinguishable from the other BRAM bits in every way.  You can use them for storing parity, but that is strictly up to you.

(1) How do I trick the CoreGen so that it does not create parity bits? I want a bram for the size of 32 x 2048 having no parity bits to worry about.

Coregen (FIFO wizard) should do that for you.

- Bob Elkind

 
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

eteam00写道：
你真的运行过FIFO发生器吗？
如果没有，那么请立即停止并运行FIFO生成器，然后再提出任何问题。
当只有数据进入而数据在另一端出来时，我真的在寻找标准的FIFO。
到目前为止听起来很正常......
我想要的几乎就像双端口存储器，输入地址和输出地址不同。
还是很正常......
换句话说，我应该可以在任何地方写入并从任何地址获取数据
你开始担心我了。
你想描述随机访问吗？
如果是这样，这不是FIFO，它是双端口RAM。
当我写入数据时，我按顺序递增地址...
地址指针在向导生成的FIFO内部。
我担心你可能已经阅读了精美的手册，但你不了解基础知识。
......几乎像一个带环绕的圆形缓冲区。
您是否需要在写入时进行环绕，因此您可以覆盖尚未读取的FIFO条目？
（超限运行）
或者您是否需要在读取时进行环绕，因此您可以读取已经获取的FIFO条目？
（下运行）
说真的，您认为FIFO发生器缺少什么？
当我读出时，输出数据地址几乎可以在RAM内
这听起来有点随意......我真的希望我们在这里遇到语言困难，而且没有比那更邪恶的了。
我不想要奇偶校验位的麻烦。
这听起来像你不理解我以前的帖子（我特别介绍了奇偶校验位的主题）。
请向我们解释您认为这意味着什么：
我认为CoreGen创造了一个带有奇偶校验位的bram。
我想要的是没有奇偶校验位的简单bram。
BRAM原语是（本机的）18位宽。
文档将18位中的2个标记为奇偶校验位，但它们在各方面都与其他BRAM位无法区分。
您可以使用它们来存储奇偶校验，但这完全取决于您。
（1）如何欺骗CoreGen以便它不会创建奇偶校验位？
我想要一个大小为32 x 2048的bram，没有奇偶校验位需要担心。
Coregen（FIFO向导）应该为您做到这一点。
- 鲍勃埃尔金德
鲍勃，
在我回信给你之前，我确实运行了Fifo Generator。
它有inputdata DIN，但没有输入地址。
我需要输入地址来读取数据。
它有输出数据DOUT，但没有输出地址。
我需要输出地址从哪里读出输出。
它有很多我不需要的旗帜。
因此它不是FIFO。
我必须是一个双端口RAM。
因此，唯一的选择似乎是块存储器生成器，它提供数据和地址字段。
使用块存储器生成器，存储器类型必须是“简单双端口RAM”。
如果未选中“使用字节写入使能”，则“字节大小”默认为9位，其中包括奇偶校验。
为避免这种情况，我必须检查“使用字节写入启用”并为“字节大小”选择8位
有了上述选项，我应该得到我想要的东西。
不知怎的块内存生成器没有给我我想要的东西。
它增加了平价。
问题是，是否有解决方法。
我希望这会使问题变得清晰。
谢谢，
胜利者



以下为原文

eteam00 wrote:
Have you actually run the FIFO generator?  If not, then please STOP NOW and run the FIFO generator before you ask any more questions.

I am really looking for a standard FIFO when there is only data going in and data coming out in the other end.

Sounds pretty normal so far...

What I want is almost like a dual port memory where the input address and output address are different.

Still pretty normal...

In other words, I should be able to write in anywhere and get the data out from any address

You're starting to worry me.  Are you trying to describe random access?  If so, this isn't a FIFO, it's a dual port RAM.

When I write the data in, I sequentially increment the address...

The address pointers are internal to the FIFO generated by the wizard.  I'm worried you may have read the fine manual, but you don't understand the basics.

... almost like a circular buffer with wrap around.

Do you require wraparound on write, so you can over-write FIFO entries which haven't been read? (over-run)
Or do you require wraparound on read, so you can read FIFO entries which have already been fetched? (under-run)
 
Seriously, what do you think you are missing from the FIFO generator?

When I read out, the out data address can be almost anything within the RAM

That sounds a bit random...  I really hope we're having language difficulties here, and nothing more sinister than that.

I don't want the hassle of parity bits.

This sounds like you did not comprehend my previous post (I specifically covered the subject of parity bits).  Please explain to us what you think this means:

I think that CoreGen has created a bram with parity bits. What I want is simple bram without parity bits.

The BRAM primitive is (native) 18 bits wide.  The documentation labels 2 of the 18 bits as parity bits, but they are indistinguishable from the other BRAM bits in every way.  You can use them for storing parity, but that is strictly up to you.

(1) How do I trick the CoreGen so that it does not create parity bits? I want a bram for the size of 32 x 2048 having no parity bits to worry about.

Coregen (FIFO wizard) should do that for you.

- Bob Elkind

 

Bob,
 
I did run Fifo Generator before I wrote back to you.
 
It has input data DIN, but no input address.  I need input address where the data will be read in.
It has  output data DOUT, but no output address. I need output address from where output will be read out.
It has a lot of flags which I don't need.
 
Hence it is not the FIFO.
 
I has to be a dual port RAM. Hence the only option seems to be Block Memory Generator which gives both data and address fields.
 
With Block Memory Generator, the memory type has to be "Simple Dual Port RAM".
If the "Use Byte Write Enable" is not checked, "Byte Size" is defaulted to 9 bits which iincludes parity. To avoid this, I have to check "Use Byte Write Enable" and select 8 bits for "Byte Size"
 
With the above options, I should get what I want. Somehow Block Memory Generator did not give me what I wanted. It added parity.
 
The question is if there is a fix for this.
 
I hope that this makes the issue clear.
 
Thanks,
Victor

使用块存储器生成器，存储器类型必须是“简单双端口RAM”。
如果未选中“使用字节写入启用”，则“字节大小”为
默认为9位，包括奇偶校验。
它是第9位，而不是奇偶校验位。
这不是问题。
您可以在下一个屏幕上选择写入和读取宽度。
为了避免这种情况，我必须这样做
选中“使用字节写入启用”并为“字节大小”选择8位
您无需选中“使用字节写入启用”。
有了上述选项，我应该得到我想要的东西。
不知怎的块内存生成器没有给我我想要的东西。
它增加了平价。
我运行了块内存生成器，这是结果（在实例化模板文件中）：
forum_bram YourInstanceName（.clka（clka）,. wea（wea），// Bus [0：0] .addra（addra），// Bus [10：0] .dina（dina），// Bus [7：0
] .clkb（clkb）,. addrb（addrb），// Bus [10：0] .doutb（doutb））;
//巴士[7：0]
请注意读取和写入端口上的数据宽度。
写使能是1位信号。
所以再试一次内存生成器，看看你得到的结果是否相同。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

With Block Memory Generator, the memory type has to be "Simple Dual Port RAM".
If the "Use Byte Write Enable" is not checked, "Byte Size" is defaulted to 9 bits which includes parity.

It's a 9th bit, not a parity bit.  This isn't a problem.  You select write and read width on the next screen.

To avoid this, I have to check "Use Byte Write Enable" and select 8 bits for "Byte Size"

You don't need to check "Use Byte Write Enable".

With the above options, I should get what I want. Somehow Block Memory Generator did not give me what I wanted. It added parity.

I ran the block memory generator, and this is the result (in the instantiation template file):

forum_bram YourInstanceName (
    .clka(clka),
    .wea(wea), // Bus [0 : 0]
    .addra(addra), // Bus [10 : 0]
    .dina(dina), // Bus [7 : 0]
    .clkb(clkb),
    .addrb(addrb), // Bus [10 : 0]
    .doutb(doutb)); // Bus [7 : 0]

Note the data width on both read and write ports.  Write enable is a 1-bit signal.

 

 

 
So try the memory generator one more time, and see if you get the same results I get.
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

eteam00写道：
使用块存储器生成器，存储器类型必须是“简单双端口RAM”。
如果未选中“使用字节写入使能”，则“字节大小”默认为9位，其中包括奇偶校验。
它是第9位，而不是奇偶校验位。
这不是问题。
您可以在下一个屏幕上选择写入和读取宽度。
为避免这种情况，我必须检查“使用字节写入启用”并为“字节大小”选择8位
您无需选中“使用字节写入启用”。
有了上述选项，我应该得到我想要的东西。
不知怎的块内存生成器没有给我我想要的东西。
它增加了平价。
我运行了块内存生成器，这是结果（在实例化模板文件中）：
forum_bram YourInstanceName（.clka（clka）,. wea（wea），// Bus [0：0] .addra（addra），// Bus [10：0] .dina（dina），// Bus [7：0
] .clkb（clkb）,. addrb（addrb），// Bus [10：0] .doutb（doutb））;
//巴士[7：0]
请注意读取和写入端口上的数据宽度。
写使能是1位信号。
所以再试一次内存生成器，看看你得到的结果是否相同。
- 鲍勃埃尔金德
嗨鲍勃，
现在你也许可以看出为什么我感到困惑。
如果我检查“使用字节写入启用”，这似乎允许“字节大小”为8.另一方面，它创建了我不想要的4位宽WEA信号。
当我编译并生成比特流时，有一个关于悬挂WEA引脚的警告。
但是bitgen创建了“成功”的位文件，从操作的角度来看这是无用的。
因为我只有1位WEA。
Bitgen跳过此警告并且不会生成错误。
因此，当我刷新FPGA时，它不起作用。
我的印象是，如果我选择“Fixed Primitives”选项，那么我将被卡在9位宽的字节中。
这就是ug331.pdf所说的，尽管CoreGen似乎与Block Memory Generator GUI所期望的完全相反。
因此，我认为必须在手册或GUI中明确所有这些设置及其确切内容。
感谢您耐心了解我的问题。
我会尝试让你知道bitgen是否标记错误。
谢谢，
胜利者



以下为原文

eteam00 wrote:

With Block Memory Generator, the memory type has to be "Simple Dual Port RAM".
If the "Use Byte Write Enable" is not checked, "Byte Size" is defaulted to 9 bits which includes parity.

It's a 9th bit, not a parity bit.  This isn't a problem.  You select write and read width on the next screen.

To avoid this, I have to check "Use Byte Write Enable" and select 8 bits for "Byte Size"

You don't need to check "Use Byte Write Enable".

With the above options, I should get what I want. Somehow Block Memory Generator did not give me what I wanted. It added parity.

I ran the block memory generator, and this is the result (in the instantiation template file):

forum_bram YourInstanceName (
    .clka(clka),
    .wea(wea), // Bus [0 : 0]
    .addra(addra), // Bus [10 : 0]
    .dina(dina), // Bus [7 : 0]
    .clkb(clkb),
    .addrb(addrb), // Bus [10 : 0]
    .doutb(doutb)); // Bus [7 : 0]

Note the data width on both read and write ports.  Write enable is a 1-bit signal.

 

 

 
So try the memory generator one more time, and see if you get the same results I get.
 
- Bob Elkind

Hi Bob,
 
Now you can perhaps see why I got confused.
 
If I check "Use Byte Write Enable ", that seems to allow "Byte Size" to be 8. On the other hand, it creates 4 bit wide WEA signal which I don't want. When I compile and generate the bitstream, there is a warning about dangling WEA pins. But bitgen creates "successfully" bit file which is useless from operational point of view. Because I have only 1 bit WEA.  Bitgen skips this warning and does not generate error. Hence when I flash the FPGA it does not work.
 
I was under the impression that if I choose the "Fixed Primitives" option, then I will be stuck with 9 bit wide bytes. That is what ug331.pdf says though CoreGen seems to do exactly opposite of what one expects from the Block Memory Generator GUI. Hence I think that all these settings and what exactly they do must be made clear in the manual or in the GUI.
 
Any way thanks for your patience in understanding my problem. I will try and let you know whether the bitgen flags an error or not.
 
Thanks,
Victor

vramamoorthy写道：
eteam00写道：
使用块存储器生成器，存储器类型必须是“简单双端口RAM”。
如果未选中“使用字节写入使能”，则“字节大小”默认为9位，其中包括奇偶校验。
它是第9位，而不是奇偶校验位。
这不是问题。
您可以在下一个屏幕上选择写入和读取宽度。
为避免这种情况，我必须检查“使用字节写入启用”并为“字节大小”选择8位
您无需选中“使用字节写入启用”。
有了上述选项，我应该得到我想要的东西。
不知怎的块内存生成器没有给我我想要的东西。
它增加了平价。
我运行了块内存生成器，这是结果（在实例化模板文件中）：
forum_bram YourInstanceName（.clka（clka）,. wea（wea），// Bus [0：0] .addra（addra），// Bus [10：0] .dina（dina），// Bus [7：0
] .clkb（clkb）,. addrb（addrb），// Bus [10：0] .doutb（doutb））;
//巴士[7：0]
请注意读取和写入端口上的数据宽度。
写使能是1位信号。
所以再试一次内存生成器，看看你得到的结果是否相同。
- 鲍勃埃尔金德
嗨鲍勃，
现在你也许可以看出为什么我感到困惑。
如果我检查“使用字节写入启用”，这似乎允许“字节大小”为8.另一方面，它创建了我不想要的4位宽WEA信号。
当我编译并生成比特流时，有一个关于悬挂WEA引脚的警告。
但是bitgen创建了“成功”的位文件，从操作的角度来看这是无用的。
因为我只有1位WEA。
Bitgen跳过此警告并且不会生成错误。
因此，当我刷新FPGA时，它不起作用。
我的印象是，如果我选择“Fixed Primitives”选项，那么我将被卡在9位宽的字节中。
这就是ug331.pdf所说的，尽管CoreGen似乎与Block Memory Generator GUI所期望的完全相反。
因此，我认为必须在手册或GUI中明确所有这些设置及其确切内容。
感谢您耐心了解我的问题。
我会尝试让你知道bitgen是否标记错误。
谢谢，
胜利者
嗨鲍勃，
你建议的解决方案不起作用！
我得到了与以前完全相同的DIPA0错误。
因此，使用2kx9原语确实会创建奇偶校验位，尽管模板文件会说明不同的故事。
我们回到原点......块内存生成器中有一个错误。
我能想到的唯一解决方法是回到检查“使用字节写入启用”并使用4位WEA并重写包装器。
如果还有其他方法，请告诉我。
谢谢，
胜利者



以下为原文

vramamoorthy wrote:

eteam00 wrote:

With Block Memory Generator, the memory type has to be "Simple Dual Port RAM".
If the "Use Byte Write Enable" is not checked, "Byte Size" is defaulted to 9 bits which includes parity.

It's a 9th bit, not a parity bit.  This isn't a problem.  You select write and read width on the next screen.

To avoid this, I have to check "Use Byte Write Enable" and select 8 bits for "Byte Size"

You don't need to check "Use Byte Write Enable".

With the above options, I should get what I want. Somehow Block Memory Generator did not give me what I wanted. It added parity.

I ran the block memory generator, and this is the result (in the instantiation template file):

forum_bram YourInstanceName (
    .clka(clka),
    .wea(wea), // Bus [0 : 0]
    .addra(addra), // Bus [10 : 0]
    .dina(dina), // Bus [7 : 0]
    .clkb(clkb),
    .addrb(addrb), // Bus [10 : 0]
    .doutb(doutb)); // Bus [7 : 0]

Note the data width on both read and write ports.  Write enable is a 1-bit signal.

 

 

 
So try the memory generator one more time, and see if you get the same results I get.
 
- Bob Elkind

Hi Bob,
 
Now you can perhaps see why I got confused.
 
If I check "Use Byte Write Enable ", that seems to allow "Byte Size" to be 8. On the other hand, it creates 4 bit wide WEA signal which I don't want. When I compile and generate the bitstream, there is a warning about dangling WEA pins. But bitgen creates "successfully" bit file which is useless from operational point of view. Because I have only 1 bit WEA.  Bitgen skips this warning and does not generate error. Hence when I flash the FPGA it does not work.
 
I was under the impression that if I choose the "Fixed Primitives" option, then I will be stuck with 9 bit wide bytes. That is what ug331.pdf says though CoreGen seems to do exactly opposite of what one expects from the Block Memory Generator GUI. Hence I think that all these settings and what exactly they do must be made clear in the manual or in the GUI.
 
Any way thanks for your patience in understanding my problem. I will try and let you know whether the bitgen flags an error or not.
 
Thanks,
Victor

Hi Bob,
 
The solution that you suggested does not work!!!  I got exactly the same DIPA0 error as before. So using 2kx9 primitives indeed creates parity bits though the template files tell a different story.
 
We are back to square one..... There is a bug in the Block Memory Generator.
 
The only fix that I can think of is going back to checking "Use Byte Write Enable" and use 4 bit WEA and rewrite the wrapper.
 
Let me know if there is any other way.
 
Thanks,
Victor

你建议的解决方案不起作用！
我完全得到了
与以前相同的DIPA0错误。
所以使用2kx9原语确实会产生
奇偶校验位虽然模板文件讲述了不同的故事。
我们回到原点......块内存生成器中有一个错误。
我能想到的唯一解决方法是回到检查“使用字节写入启用”并使用4位WEA并重写包装器。
胜利者，
这令人失望。
如果您能够等待一天，那么让我们为这个论坛中的知识渊博的人们提供一个解决问题的机会。
它可能很简单。
如果没有任何帮助，那么是时候打开一个webcase来确认并纠正问题。
在家政记录上，没有必要在每次“回复”时“引用”一组大图片和文字。
修剪掉不需要的东西很有帮助。
这样可以节省时间和空间，并有助于将注意力集中在新的有用部件上。
论坛版主给用户：请KUDO，请接受解决方案。
不是我，是帮助你的人。
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

The solution that you suggested does not work!!!  I got exactly the same DIPA0 error as before. So using 2kx9 primitives indeed creates parity bits though the template files tell a different story.
 
We are back to square one..... There is a bug in the Block Memory Generator.
The only fix that I can think of is going back to checking "Use Byte Write Enable" and use 4 bit WEA and rewrite the wrapper.

Victor,
 
That's disappointing.
 
If you can afford to wait a day, let's give the knowledgeable folks in this forum an opportunity to troubleshoot the problem.  It could be something simple.  If nothing helps, then it's time to open a webcase to confirm and correct the problem.
 
On a housekeeping note, it is not necessary to 'quote' a big honkin' set of images and text every time you 'reply'.  It's helpful to trim out the stuff that's not needed.  This saves time and space, and helps focus attention on the new and useful parts.
Forum moderator to users:  Please KUDO, and please Accept Solution.  Not me, the guy who HELPED you.SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.