是否需要为所有数据通道制作一个通用的相位检测器状态机？

注意：我的一些ISERDES2 DDR模式操作的技术说明在本主题的后续帖子中被用户pml（Philippe）质疑。
这篇文章中有关问题的具体要点以红色标出。
我建议任何读到这篇文章的人都认为Philippe的洞察力和经验超过了我的，应该被认为更可靠。
- 鲍勃埃尔金德
我有26个LVDS数据通道和1个时钟LVDS通道输入，来自180 Mhz DDR，我正在进行5到1的反序列化。
如果您正在使用DDR时钟，则可以执行4：1,6：1或8：1反序列化。
在DDR模式下，5：1不是一个选项。
如果你在DDR时钟模式下使用BITSLIP，你将一次BITSLIPping 2位（一个IOCLK周期）。
（注意：在阅读Philippe的帖子后，这一整段应该受到质疑 -  Bob）
我打算使用不同的状态机进行相位检测
所有26个LVDS数据通道的通用bitlip状态机。
这是 
接近有效或fpga证明？
是。
我需要做一个共同的阶段吗？
所有数据通道的探测器状态机？
你可以这样做，但你可能不想这样做。
您的26个串行输入相互之间的对齐程度如何？
您的（聚合）数据眼图有多宽？
一定要尝试单主延迟调整方法。
如果您的无差错接收调整窗口太小（或不存在），那么您就需要进行独立的输入延迟调整。
使用DDR模式的唯一优势是避免使用PLL将0.5x比特率输入时钟乘以1x（SDR）比特率时钟。
DDR输入时钟没有其他优势。
使用SDR时钟（并使用PLL）可以获得很大的优势：IOCLK与输入时钟的相位对齐。
您可以使用两种数据到时钟的调整：
时钟输入延迟（影响所有输入的时序）
数据输入延迟（输入到IOCLK的个别偏差）
您应该考虑是否需要或希望进行这些时序调整，以及您希望使用它们的程度。
如果您决定对所有26个输入使用单个调整状态机，则可以选择仅控制串行时钟输入延迟而不是26个串行输入。
净结果应该相同（添加数据输入的延迟完全等同于消除时钟输入的延迟）。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

NOTE: Some of my technical description of ISERDES2 DDR mode operation is called into question by user pml (Philippe), in a followup post in this thread.  The specific points in this post which are called into question are marked in RED.  I suggest to anyone reading this that Philippe's insight and experience outweighs mine, and should be considered more reliable.  - Bob Elkind

I have  26 LVDS data channel and 1 clock LVDS channel inputs coming at 180 Mhz DDR, I am doing a 5 to 1 deserialization.

If you're using DDR clocking, then you can do 4:1, 6:1, or 8:1 deserialisation.  5:1 is not an option in DDR mode.
If you use BITSLIP in DDR clocked mode, you'll be BITSLIPping 2 bits (one IOCLK cycle) at a time. (note:  after reading Philippe's post, this entire paragraph should be called into question - Bob)

I am planning to use different state machines for phase detector and common bitslip state machine for all the 26 LVDS Data channels.  Is this approach valid or fpga proven?

Yes.

Do I need to make a common phase detector state machine for all the data channels?

You can do this, but you may not want to do this.  How well-aligned are your 26 serial inputs to each other?  How wide is your (aggregate) data eye pattern?  By all means try the single master delay adjust approach.  If your adjust window for error-free reception is too small (or non-existent), that's your clue that you need independent input delay adjustments.
 
The only advantage of using DDR mode is avoiding the use of a PLL for multiplying the 0.5x bit rate input clock to 1x (SDR) bit rate clock.  There are no other advantages to DDR input clocking.  You get a big advantage with SDR clocking (and using a PLL):  phase alignment of IOCLK to input clock.
 
You have two data-to-clock adjustments available to you:

• Clock input delay (affects timing of all inputs)
  
• Data input delay (individual de-skew of input to IOCLK)
  

You should consider whether you need or want these timing adjustments, and the extent to which you want to use them.  If you decide to use a single adjustment state machine for all 26 inputs, you have the option of controlling just the serial clock input delay rather than the 26 serial inputs.  The net result should be the same (add delay to data input is entirely equivalent to remove delay on clock input).
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

非常感谢鲍勃。
今天早上，我可以使用spartan xc6slx75正确地通过26个通道接收测试模式，每个通道使用不同的相位检测器和常见的bitlipping。 
关于校准，我使用差分相位检测器模式每256个时钟周期校准它似乎现在工作，但我不确定它是否安全



以下为原文

 
  Thank you very much Bob.  This morning I can be able receive test pattern through 26 channels correctly using spartan  xc6slx75 using different phase detectors for each channel and common bitslipping. 
 
  About calibration,  I am calibrating every 256 clock cycles using diff phase detector mode its seems to work for now but I am not sure still whether it is safe or not
 

>关于校准，我使用diff校准每256个时钟周期
它似乎是相位检测器模式
>现在工作，但我不确定
是否安全
校准功能与DIFF_PHASE_DETECTOR模式一起不会影响数据流，因为您已经阅读并在原始帖子中注明了......“用于避免数据丢失。”
但是，每256个周期校准是非常不必要的，并且不允许DIFF_PHASE_DETECTOR部分工作，并且将数据延迟设置始终保持在HALF_MAX点，因为在下一次校准和复位之前没有任何时间进行调整。
除非您预期温度变化范围很广，否则每小时校准一次应该是足够的。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

> About calibration,  I am calibrating every 256 clock cycles using diff phase detector mode its seems to
> work for now but I am not sure still whether it is safe or not
 
The calibration function in conjunction with the DIFF_PHASE_DETECTOR mode will not impact the data stream as you already read and noted in your original post  ....  "and is used to avoid data loss."
 
However, calibrating every 256 cycles is very unnecessary and would not allow the DIFF_PHASE_DETECTOR portion to operate and will leave the data delay settings always at the HALF_MAX point as it will not have any time to adjust before the next calibration and reset.  Calibrating once an hour should be more than adequate unless you expect to have wide ranging temperature changes.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

“每小时校准一次应该是足够的，除非你期望温度变化很大。” 
好的我会这样做，但我心中只有一个问题。
问题：xapp1064的参考设计文件包括vhd文件serdes_1_to_n_data_sX_diff.vhd。
在此模板中，有一个状态机每隔256个时钟周期向从机发送校准信号。
选择这个数字256是有原因的吗？
或者我很抱歉，我非常忽视和误解了一些事情。
因为1小时和256个时钟周期之间存在巨大差异。
==================================================
======================================
为什么我这样结束： 
在ug381.pdf中写道
状态机需要定期重新校准SLAVE延迟以确保作为
延迟线值随电压和温度漂移，不会发生数据损坏。
这是通过仅向SLAVE IODELAY2发出CAL命令来实现的;
然后该单元校准自己，
根据我的理解，上述声明意味着只需将CAL发送到从站就足以进行以下校准。
当我搜索向客户端发送CAL的机制时，我发现了一个计数器和状态机。
在参考设计文件中，有一个计数器，每个时钟周期递增一次，当计数器（8）= 1时，计数器变为0.该计数器与状态机一起发送校准信号到从属IODELAY。
当计数器（8）= 1时，状态变为5并且从属被校准。
==================================================
===================================



以下为原文


"Calibrating once an hour should be more than adequate unless you expect to have wide ranging temperature changes."
  Ok I wil do this but I do have only 1 question in my mind.
 
 Question: Reference design files of xapp1064, includes the vhd file serdes_1_to_n_data_sX_diff.vhd.  In this template, there is a state machine that sends calibration signals to slave every 256 clock cycles.  Is this number 256 chosen for a reason? Or  My apologies since, I am extremely overlooking and missunderstanding something.  Because there is a huge difference between 1 hour and 256 clock cycles.
 
========================================================================================
why I conclude like this:




 From my understanding the above statement means just sending CAL to slave is enough for the following calibrations. When I search for the mechanism that sends CAL to slave I found a counter and state machine.  In the reference design file there is a counter that increments every clock cycle and goes to 0 when counter(8) = 1.  This counter is in conjunction with the state machine that sends calibrate signal to slave IODELAY.  State becomes 5 and slave is calibrated when the counter(8) = 1.
=====================================================================================
 

鲍勃，
你是什​​么意思：“如果你在DDR时钟模式下使用BITSLIP，你将一次BITSLIPping 2位（一个IOCLK周期）”
我在DDR模式下的经验是，一个bitlip脉冲（在1 DIVCLK周期内有效）将输出移位一位。
例如，DDR模式，x8反序列化，0101010 ...模式将在02020202 ...单位移位后。
你同意吗 ？
菲利普。



以下为原文

Bob,
 
What do you mean by : "If you use BITSLIP in DDR clocked mode, you'll be BITSLIPping 2 bits (one IOCLK cycle) at a time"
 
My experience in DDR mode is that one bitslip pulse (active during 1 DIVCLK cycle) will shift the output by one bit.
For exemple, DDR mode, x8 deserialization, 0101010... pattern will be 02020202... after a single bit shift.
 
Do you agree ?
 
Philippe.
 

你是什​​么意思：“如果你在DDR时钟模式下使用BITSLIP，你将一次BITSLIPping 2位（一个IOCLK周期）”
我在DDR模式下的经验是，一个bitlip脉冲（在1 DIVCLK周期内有效）将输出移位一位。
例如，DDR模式，x8反序列化，0101010 ...模式将在02020202 ...单位移位后。
我在DDR模式下没有BITSLIP的个人经验。
我的“理解”（或缺乏）基于UG381（其中以DDR模式运行的ISERDES2的覆盖范围非常稀疏），关于BITSLIP主题的论坛主题以及关于BITSLIP主题的电子邮件交换。
而且我添加了一些我自己的猜想。
为了使BITSLIP在DDR模式下滑动单个位，IOCLK输入时钟必须在ISERDES2模块内加倍。
这听起来似乎是合理的，并且在各种文档中都有一些倾向性的参考。
如果这个（ISERDES2的内部时钟加倍，而BUFIO2中的时钟加倍 - 相对于CLKDIV和SERDESSTROBE输出），那么我对DDR模式下ISERDES2操作的理解是完全错误的。
Philippe，我尊重你在DDR模式操作方面的个人经验，而且我没有任何理由与你所说的相矛盾。
我将在之前的帖子中添加注释，这些帖子会引用您的帖子，并添加一些注释，表明我对某些技术要点的“确定性”是过度陈述的，并且基于猜想而不是洞察力。
感谢您关于此主题的后续发布。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

What do you mean by : "If you use BITSLIP in DDR clocked mode, you'll be BITSLIPping 2 bits (one IOCLK cycle) at a time"
 
My experience in DDR mode is that one bitslip pulse (active during 1 DIVCLK cycle) will shift the output by one bit.
For exemple, DDR mode, x8 deserialization, 0101010... pattern will be 02020202... after a single bit shift.

I have no personal experience with BITSLIP in DDR mode.  My "understanding" (or lack thereof) is based on UG381 (in which the coverage of ISERDES2 operating in DDR mode is VERY sparse), forum threads on the subject of BITSLIP, and email exchanges on the subject of BITSLIP.  And I've added some conjecture of my own.
 
In order for BITSLIP to slip a single bit position in DDR mode, the IOCLK input clock must be doubled inside the ISERDES2 block.  This sounds entirely plausible, and there are some oblique references to that in the various docs.  If this (clock doubling internal to ISERDES2, and in BUFIO2 -- with respect to CLKDIV and SERDESSTROBE outputs), then my understanding of ISERDES2 operation in DDR mode is completely wrong.
 
Philippe, I defer to your personal experience with DDR mode operation, and I have no basis for contradicting what you say.
 
I will add notes to my previous post which refer to your post, and add some notes that my "certainty" on some technical points is over-stated and based on conjecture rather than insight.
 
Thank you for the follow-up post on this subject.
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

鲍勃，
我仔细检查并确认我写的内容。
至少从仿真的角度来看：在DDR模式下，1位压缩脉冲 - >数据输出上的1位移位。
如果在仿真中这样工作就像这样，那么硅会不会有同样的疑问？
我希望不是因为这可能会对我的项目产生重大影响......
菲利普。



以下为原文

Bob,
 
I double check and confirm what I wrote. At least from a simulation point of view : in DDR mode, 1 bitslip pulse --> 1 bit shift on the data output. 
 
If that works like this in simulation, any doubts that silicon will do the same ?
I hope not because this may have major impact on my project...
 
Philippe.
 

我仔细检查并确认我写的内容。
至少从模拟中
观点：在DDR模式下，1位滑动脉冲 - > 1位移位
数据输出。
如果在仿真中这样工作就像这样，那么硅会不会有同样的疑问？
我希望不是因为这可能会对我的项目产生重大影响......
我重新阅读的UG381和UG382越多，我就越相信你的理解是正确的，Philippe。
您应该相信模拟结果是ISERDES2硬件的代表。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

I double check and confirm what I wrote. At least from a simulation point of view : in DDR mode, 1 bitslip pulse --> 1 bit shift on the data output. 
 
If that works like this in simulation, any doubts that silicon will do the same ?
I hope not because this may have major impact on my project...

The more I re-read UG381 and UG382, the more I believe your understanding is correct, Philippe.  You should trust the simulation results as being representative of the ISERDES2 hardware.
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

亲爱的BOB和其他人，
我不知道我是否应该为此开启另一个话题，因为我的设计是2天前经过验证的，我已经得到了我的问题的答案，除了这个神秘的256 :)
目前我的设计与26个数据通道正常工作。
感谢PCB工程师，我需要从2个不同的银行激活4个以上的数据通道。
当然，ISE Placer会给出如下错误，因为bufplls可以驱动单个库。
1- 
我有什么选择？
我不想改变这种PLL方法，因为
它在26个频道上运行得相当不错（实际上我首先进行1到5次反序列化，然后是5到10次，它正在工作，我很害怕改变它）。
有没有一个安全/快速的解决方案，如在另一个银行实例化另一个bufpll，其输入与其他bufplls相同。
ERROR =================================================
================================ 
BUFLL / BUFPLL_MCB实例X.
需要将其所有IOB负载放入同一个IO bank中。
但是，由于用户指定的约束，BUFLL / BUFPLL_MCB
实例X及其IOB加载data_in_p_27不能放在同一个中
IO银行。
这些约束可能是X上的LOCATION或AREA约束，
或data_in_p_27，或连接到它们的其他组件，可以
对它们施加隐含约束。
请检查用户指定的
限制所有这些组件以确保它们的组合
不可行。
==================================================
====================================



以下为原文

  Dear BOB and others,
 
I do not know if I should open another topic for this because My design is fpga proven 2 days ago and I already got my answers to my questions except this mysterious 256 :)
 
Currently my design is working correctly with 26 data channels. Thanks to PCB engineer,  I need to activate 4 more Data channels from 2 different banks. Of course ISE Placer gives an error as below because the bufplls can drive single banks.
 
1- What are my options? I do not want to change this PLL approach because it is working quite good on 26 channels (Actually I am doing 1 to 5 deserialization first and then 5 to 10 and it is working and I am scared to change this). Is there a safe/quick solution for this like instantiating another bufpll on another bank whose inputs are the same with the other bufplls.
 
 


ERROR=================================================================================
  
The BUFLL/BUFPLL_MCB instance X needs to have all of its IOB loads placed into its same IO bank. However, due to user-specified  constraints, the BUFLL/BUFPLL_MCB instance X and its IOB load  data_in_p_27 cannot be placed in the same IO bank. These constraints could be LOCATION or AREA constraints on X, or data_in_p_27, or other components connected to them, which could impose an implicit constraint on them. Please check user-specified constraints on all of these components to ensure their combination is not infeasible. 
======================================================================================