专用乘法器不适用于FPGA

问题：专用乘法器不适用于FPGA而是模拟
工作正常。
我试过的：
在我的一个设计中，我使用10x10bit乘法器。
原来我只是
使用w6 = Vout * Vout。
在模拟中，这似乎适用于我的设备
利用率总结它表明使用了4个MULT18X18SIO中的1个。
一旦在FPGA上实现了设计，我就发现了乘法器
实际上只使用8x8bit乘法。
经过一番阅读后我发现你可以直接控制了
MULT18X18SIO具有以下Verilog模块：http：//www.xilinx.com/support/documentation/user_guides/ug331.pdf
第385页。
模块mult18x18sio（
输入[7：0] a，
输入[7：0] b，
输入clk，
输出[15：0] prod
）;
reg [15：0] prod;

总是@（posedge clk）prod 以下为原文

Problem: Dedicated multiplier does not work on FPGA but simulationworks fine.

What I have tried:

In one of my designs I use a 10x10bit multiplier. Originally I justused w6=Vout*Vout. In simulation this seemed to work and in my deviceutilization summary it states that 1 of 4 MULT18X18SIOs is used.

Once the design was implemented on the FPGA I found that the multiplieris actually using only 8x8bit multiplication.

After some reading I found that you can directly control theMULT18X18SIO with the following module for Verilog found here: http://www.xilinx.com/support/documentation/user_guides/ug331.pdfon page 385.
module mult18x18sio(
    input [7:0] a,
    input [7:0] b,
    input clk,
    output [15:0] prod
    );
                 reg [15:0] prod;
                 always @(posedge clk) prod <= a*b;
endmodule

Page 386 of the same manual states that you must enable themult_style=block setting. I have been unable to find this setting selection inISE design Suite v11.1.

I also found a statement that says you can use  (* mult_style = "{block}" *) to setthe mult_style in code, however when I try to use this just before I call the mult18x18sio,I get a warning from synthesizing saying that the selection block is not availablefor the mult_style parameter.

I am also having trouble getting the module to import or run with mydesign.  When trying to add the module Iam going to [Project] [New Source] then select [Verilog module] enter the nameof the module and fill out the parameter information as seen above. When I callthe module in my main design I do the following: mult18x18siomult1(Vout,Vout,clk,w6); but get an error stating that it could not find themodule/primitive  ‘mult18x18sio’

I am new to Verilog, ISE design suite, and FPGA’s in general. Any helpyou could provide would be appreciated. If you require a simple example of mydesign, and how I am implementing the multiplication please let me know and Iwill post it.