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你好，
我试图使用flash PROM xcf04s在主串行模式下配置我的FPGA xc3s500e。 我使用Xilinx 12.1 for Linux生成.bit和.mcs文件。 我使用带有iMPACT的USB电缆对闪存PROM进行了编程，但之后没有配置fpga。 我错过了什么？ 下一个命令用于生成文件： bitgen -w -g StartupClk：CCLK -g Binary：yes -g ConfigRate：25 file.ncd file.bit promgen -w -c FF -p mcs -u 0 file.bit -x xcf04s 我编写了闪存PROM，按下了PROG按钮，但DONE LED没有亮起。 我通过iMPACT读取了fpga寄存器的属性 - > Debug - > Read Device Status： 信息：iMPACT - 当前时间：vie ago 13 13:42:47 2010 // *** BATCH CMD：ReadStatusRegister -p 1此设备链的最大TCK工作频率：1000000.Validating chain ...边界扫描链验证成功 .'1'：读取状态寄存器内容... CRC错误：0解密器安全设置：0DCM锁定：1DCI匹配：1传输输入错误：GTS_CFG_B的0状态：GWE的0状态：GHIGH的0状态：MODE引脚的0值M0：MODE的0值 引脚M1：MODE引脚M2的0值：CFG_RDY（INIT_B）的0值：来自DONE引脚的1DONEIN输入：0IDCODE在尝试写入FDRI时未验证：0write在解密操作之前或之后发出的FDRI：0Decryptor键未按正确顺序使用：0 谢谢。 以上来自于谷歌翻译 以下为原文 Hello, i have tried to configure my fpga xc3s500e in Master Serial Mode using the flash PROM xcf04s. I generate the .bit and .mcs files using Xilinx 12.1 for Linux. I programmed the flash PROM using the USB cable with iMPACT, but the fpga is not configurated after that. What i have missed? The next commands were used to generate the files: bitgen -w -g StartupClk:CCLK -g Binary:yes -g ConfigRate:25 file.ncd file.bit promgen -w -c FF -p mcs -u 0 file.bit -x xcf04s I programmed the flash PROM, pushed the PROG push-button but the DONE LED doesn't lights up. I read the estate of the registers in the fpga with iMPACT -> Debug -> Read Device Status: INFO:iMPACT - Current time: vie ago 13 13:42:47 2010 // *** BATCH CMD : ReadStatusRegister -p 1 Maximum TCK operating frequency for this device chain: 1000000. Validating chain... Boundary-scan chain validated successfully. '1': Reading status register contents... CRC error : 0 Decryptor security set : 0 DCM locked : 1 DCI matched : 1 legacy input error : 0 status of GTS_CFG_B : 0 status of GWE : 0 status of GHIGH : 0 value of MODE pin M0 : 0 value of MODE pin M1 : 0 value of MODE pin M2 : 0 value of CFG_RDY (INIT_B) : 1 DONEIN input from DONE pin : 0 IDCODE not validated while trying to write FDRI : 0 write FDRI issued before or after decrypt operation : 0 Decryptor keys not used in proper sequence : 0 Thank you. 
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C，
http://www.xilinx.com/itp/xilinx10/books/docs/dev/dev.pdf 第323页...... 此配置的最大配置速率为1 MHz，因此对于ConfigRate，正确的-g选项为1，而不是25。 Austin Lesea主要工程师Xilinx San Jose 以上来自于谷歌翻译 以下为原文 c, http://www.xilinx.com/itp/xilinx10/books/docs/dev/dev.pdf page 323... The max config rate for this is 1 MHz, so the correct -g option is 1, not 25 for ConfigRate. Austin Lesea Principal Engineer Xilinx San Jose |
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你好，谢谢你的回答，
我试过这个命令： bitgen -w -g StartupClk：CCLK -g Binary：yes -g ConfigRate：1 file.ncd file.bit promgen -w -c FF -p mcs -u 0 file.bit -x xcf04s 但设备状态没有变化，DONE LED不亮。 我尝试在Flash PROM上执行ReadBack，它看起来与原始.mcs文件完全相同。 以上来自于谷歌翻译 以下为原文 Hello, thanks for answer, I have tried with this commands: bitgen -w -g StartupClk:CCLK -g Binary:yes -g ConfigRate:1 file.ncd file.bit promgen -w -c FF -p mcs -u 0 file.bit -x xcf04s but there are no change in the device status and the DONE LED doesn't lights up. I tried to do ReadBack on the flash PROM, and it look identical to the original .mcs file. |
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状态寄存器中的GHIGH位为0，这是CRC校验通过后释放的第一位。
如果没有达到该过程的这一步骤，则可能是SYNC字未被注册。 我们在此过程中的下一个线索是，在收到SYNC字后CCLK将加速。 调整CCLK的范围，看看配置开始后该信号是否加速。 如果这不会增加频率，则SYNC字不会进入设备。 您还可以在空白设备上运行iMPACT中的验证，然后在发生故障后运行您的部件。 如果差异数相同，则设备仍为空白。 您还可以回读PROM并确保.mcs文件仍然正常。 用于编程舞会的设置也可能存在问题，例如时钟选项。 AR 34104（配置设计助手）中还有更多有用的功能。 以上来自于谷歌翻译 以下为原文 The GHIGH bit is 0 in the status register and this is the first bit released after the CRC check has passed. If this step of the process is not being reached there is a possiablitiy the SYNC word isn't being registered. The next clue we have in the process is that the CCLK will speed up after the SYNC word is received. Scope the CCLK and see if this signal speeds up after configuration starts. If this does not increase frequency than the SYNC word isn't getting into the device. You can also run a Verify in iMPACT on a blank device and then on your part after the failure. If the number of differences are the same the device is still blank. You can also readback the PROM and make sure the .mcs file is still in tact. There could also be an issue with the setting used to program the prom such as the clocking option. There is also more useful sugestions in AR 34104, the Configuration Design Assistant. |
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我们似乎有一个看起来很相似的问题。
在我们的情况下，当舞会编程时，10次中有9次都可以。 十分之一的舞会看起来相同（回读和检查md5sum），但FPGA只是没有编程。 你有没有解决过这个问题？ 以上来自于谷歌翻译 以下为原文 We seem to have a problem that looks very similar. In our case 9 times out of 10 when the prom is programmed all is OK. 1 time in 10 the prom looks identical (readback and check md5sum) but the FPGA just doesn't program. Did you ever solve the problem? |
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davidshand，
你应该开始一个新线程。 我们无法确定此线程中描述的原始问题对您所看到的问题有任何影响。 你的问题描述不清楚。 您是否遇到了对板载配置存储器进行编程的问题，或者您是否遇到了从配置存储器中进行FPGA自配置的问题？ - 鲍勃埃尔金德 签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。 阅读手册或用户指南。 你读过手册了吗？ 你能找到手册吗？2。 搜索论坛（并搜索网页）以寻找类似的主题。 不要在多个论坛上发布相同的问题。 不要在别人的主题上发布新主题或问题，开始新的主题！5。 学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。 提供有用的详细信息（请与网页，数据表链接）.7。 您的代码中的评论不需要支付额外费用。 我没有支付论坛帖子的费用。 如果我写一篇好文章，那么我一无所获。 以上来自于谷歌翻译 以下为原文 davidshand, 1. You should start a new thread. it is by no means certain that the original problem described in this thread has any bearing at all on the problem you are seeing. 2. You problem description is unclear. Are you having a problem with programming the onboard configuration memory, or are you having a problem with FPGA self-configuring from the configuration memory? -- Bob Elkind SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. |
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此外，添加你可以做到这一点。
1 - 在Bitgen中创建.msk文件 2 - 运行iMPACT当FPGA为空时在FPGA上验证并记下差异的数量。 3 - 运行iMPACT配置失败后验证FPGA，并查看差异数是否与空白设备相匹配。 这将告诉您是否有任何数据进入设备。 CCLK上存在基于系统的probalby噪声，并且仅基于baord上的其他事件发生。 串联电阻或分离戴维宁可能有助于时钟引脚。 以上来自于谷歌翻译 以下为原文 Also, to add you can do this. 1 - Create a .msk file in Bitgen 2 - Run iMPACT Verify on the FPGA when the FPGA is blank and note the number of differences. 3 - Run iMPACT Verify of the FPGA after a config failure and see if the number of differences matches a blank devcie. This will tell you if any data is getting into the device. There is probalby noise on the CCLK that is system based and only occuring based on other events on the baord. A series resistor or split thevenin may help on the clock pin. |
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