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将数据延迟至少与时钟边沿一样多的周期
检测电路提供保持时间。
或者如果你知道的话
输入时钟周期，您可以为时钟添加额外的延迟
同步器在此之前带来时钟使能脉冲
下一个时钟边缘。
然后你不需要添加额外的
延迟数据。
在Verilog中同步时钟很简单：
总是@（posedge sysclk）newclk 以下为原文
When synchronizing both clock and data, you need to be sure
to delay the data at least as many cycles as the clock edge
detection circuit to provide hold time. Alternately if you know the
input clock period, you could add extra delay to the clock
synchronizer to bring the clock enable pulse just before
the next clock edge. Then you don't need to add additional
delay on the data.
Synchronizing a clock in Verilog is simple:
always @ (posedge sysclk) newclk <= extclk; // no need for if / else statements
For really slow inputs (for example 100 KHz I2C) I typically add a de-glitcher to
all inputs like:
reg [2:0] isr;
reg deglitched_in;
always @ (posedge sysclk)
begin
isr <= {isr[1:0],ext_input};
if (isr == 3'b111) deglitched_in <= 1;
else if (isr == 3'b000) deglitched_in <= 0;
end
Using the same de-glitcher on data and clock keep the delays similar,
but normally this is not an issue with very slow interfaces since the data
capture is typically at the opposite edge of the clock from the data transition.
Also note that I sy the delays are similar, but they are not necessarily equal
because when a signal bounces or glitches during a transition, this delays
the output of the deglitcher.
As for why adding a LUT between the IBUF and the BUFG removes the place error,
the error is not "real" in the sense that it is impossible to do the routing you asked for.
Any source inside the fabric of the FPGA can route to a BUFG input. The "error"
used to be a warning in earlier versions of ISE. You can demote it to a warning
in the new versions using CLOCK_DEDICATED_ROUTE as noted in the error
message. The reason that routing a non-GC pin to a BUFG is now considered
an error is that the clock timing will depend on non-dedicated routing resources
and therefore will cause sampling problems, usually hold time errors. Further
the delay from the external pin to the internal global clock net can change between
builds unless you also place directed routing constraints on the input net. You don't
get the error when routing an internal fabric source to a BUFG because the
tools no longer consider this to be a clock that has phase relationship requirements
to the external pins of the FPGA.
-- Gabor
-- GaborView solution in original post
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