相位噪声如何与频率稳定性相关？

费萨尔
DCM不是PLL：它是一个全数字DSP，使用抽头延迟线来合成新频率。
抖动（相位噪声）完全是由于抽头运动造成的。
工具提供的估算基于校准曲线，适合实际测量。
使用预测松弛的工具。
你的公式来自哪里？
输入时钟源抖动输入到工具，以及“系统抖动”。
然后工具计算其他所有东西。
系统抖动是所有切换源产生的抖动，以及旁路效率。
这个数字可能从小至100 ps（对于完全同步设计，具有单个时钟）到高达1000 ps（或更多：多个时钟，大量IO切换严格，不良旁路等）。
PLL可以用于清除DCM的输出，因为DCM抖动的频率功率谱都处于非常高的频率（>> 1 MHz）并且PLL的极点低于该值。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Faisal,
 
The DCM is not a PLL:  it is a fully digital DSP using a tapped delay line to synthesize new frequencies.  The jitter (phase noise) is completely due to tap movement.
 
The estimates provided by the tools are based on calibrated curves, fit to actual measuremnts.  Use the tools the predict the slack.  Where did your formula come from?
 
The input clock source jitter is input to the tools, along with 'system jitter'.  Then the tools calculate everything else.
 
System jitter is the jitter generated by all sources of switching, and your bypass effectiveness.  This number may vary from as small as 100 ps (for a completely synchronous design, with a single clock) to as much as 1000 ps (or more:  many clocks, large number of IOs switching striongly, poor bypassing, etc.).
 
A PLL may be used to clean up the output of the DCM, as the frequency power spectrum of the DCM jitter is all at very high frequencies (>>1 MHz) and the poles for the PLL are below this value.
 
Austin Lesea
Principal Engineer
Xilinx San Jose

非常感谢奥斯汀的解释
你的公式来自哪里？
http://www.cmoset.com/uploads/4a.7.09.pdf
我不确定来源的来源。
我也见过其他论文中使用的类似公式。
我也不清楚DCM使用的频率合成。
使用DCM的时钟偏移消除是明确的。
但是我不确定为什么在延迟元件通过FPGA内部的寄存器之后时钟被抽头以获得偏斜然后通过将输入时钟与偏斜时钟进行比较来校正偏斜。
CLK0信号通过时钟分配网络传递到它同步的所有寄存器。
这些寄存器位于FPGA的内部或外部
这个外部注册表意味着什么？
。
此外，一旦DCM将锁定输出设为高电平，此后是否会发生偏斜消除？
我的意思是，只要FPGA从时钟源馈送，偏移消除过程就会运行吗？
如果该过程继续并且CLKFB和CKIN之间的比较是完美的，那么DCM不会引入任何抖动？
。
我对么 ？
还有一个简单的要求是，是否有可能理解SPARTAN 3中使用的数字频率合成背后的理论？
我已经考虑了DCM在最坏情况下引入的1000 ps抖动作为参考。
此抖动也不是累积的。
另外如果DCM能够转换完美的倍频，那么问题是，是否需要购买昂贵的高频振荡器。
例如，通过购买10 MHz振荡器，我们可以使用DCM实现100 MHz。
亲切的问候
费萨尔



以下为原文

Many Thanks Austin for the explanation
 
Where did your formula come from?.
 
http://www.cmoset.com/uploads/4a.7.09.pdf
 
 
I am not sure about the origin of the source. I have seen similar formula used in other papers as well . Also  I have no clue about the freqency synthsis used by DCM.
 
Clock skew eliminaton using DCM is clear. However I am not sure why the clock tapped after the delay element is passed through the registers inside FPGA to get skew then correct the skew by comparing input clock against skewed clock .
 
The CLK0 signal is passed through the clock distribution network to all the registers it synchronizes. These registers
are either internal or external to the FPGA
 
What does this external register means ? . Also once DCM gives locked output   high , after that is there any skew elimination takes place ? What I mean  is  Does the  skew elimination process runs as long as FPGA is feed from clock source ?

 
If the process continues  and the comparison between CLKFB and CKIN is perfect , then there will not be any jitter introduced by DCM ? . Am I correct ?

 
Also a humble request is is there any possibility to understand about theory behind digital frequency synthesis used in SPARTAN 3 ?
 
I have consdered the 1000 ps jitter introduced by DCM in worstcase as a referrence. Also this jitter is not cumulative.
 
Also  If  DCM can able to convert perfect  frequency multiplication , then kind question is , is there any need to buy expensive  high frequency oscillator. For e.g by buying a 10 MHz oscillator we can achieve 100 MHz using DCM.
 
Kind Regards
 
Faisal

 


 
 
 
 

费萨尔
该公式不适用于DCM，它是经典的模拟倍频公式。
外部参考FGPA之外的任何DFF。
例如，外围设备或外部触发器组在一些其他设备中触发，例如存储器控制器或存储器芯片。
LOCK为高电平后，数据手册中会列出最大偏差（+/- 100 ps？），直到时钟输入停止或器件发生故障。
DCM始终存在抖动。
它至少为+/- 1抽头（35ps），在2X输出上，加倍，在CLKFX输出上，看到基于M和D的预测工具（我们的工具，我们的公式，而不是错误的
你指的是）。
您可以在线查找DCM（USPTO）的专利。
寻找Xilinx，并命名为Lesea。
你会发现其他发明者发明的一些，其他人的观点。
不，我不会告诉您DCM如何比已经打印的更好，以及在专利局发布的内容。
DCM无法满足您的需求的唯一原因是增加的抖动太大，会影响您的时序预算，或影响您的应用程序（某些数字视频标准不能超过一定数量的指定抖动。
此外，抖动会直接减少A / D转换器的“有效位”数量，因此如果抖动降低了Efnob（有效的位数），请注意不要使用DCM驱动A / D.
另一个常见的初学者错误是，人们未能意识到可以使用一个DCM中的所有DCM outptus。
我见过使用许多DCM的设计，每个DCM都有一个输出，其中所有时钟都可以由单个DCM生成。
您可以连接输出，直到结构中的全局时钟用完为止，
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Faisal,
 
The formula does not apply to the DCM, it is a classic analog frequency multiplier formula.
 
External referes to any DFF outside of the FGPA.  For example, a peripheral device, or an external set of flips flops in some other device, like a memory controller, or a memory chip.
 
After LOCK is high, the max skew is listed in the data sheet (+/- 100 ps?), until the clock input stops, or the device fails.
 
There is jitter introduced by the DCM, always, forever.  It is at least +/- 1 tap (35ps), and on the 2X output, double that, and on the CLKFX outputs, see the tools for the prediction based on M and D (our tools, our formulas, not the wrong one you refer to).
 
You may look up the patents, on line, for the DCM (USPTO).  Look for Xilinx, and names Lesea.  You will find some, that point to others, invented by other inventors.  No, I will not tell you how the DCM works any further than what is already printed, and what is published at the patent office.
 
The only reason why the DCM would not be able to meet your needs, is that the added jitter is too great, detracks from your timing budget, or affects your application (certain digital video standards can not have more than some amount of specified jitter.  Also jitter directly reduces the number of 'effective bits' of an A/D converter, so be careful not to drive an A/D with a DCM if the jitter reduces the Efnob (effective nuber of bits).
 
Another common beginner error, is that people fail to realize ALL DCM outptus may be used, from one DCM.  I have seen designs where many DCMs are used, each having one output, where all the clocks could have been generated by a single DCM.  You can connect up the outputs until you run out of global clocks in the fabric,
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose