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嗨,我在PSoC3上玩ADC,我有CY8CKIT-030。我的问题是,即使我把输入GPIO(P4.6)连接到VSSA,RAWEVE也非常粗糙。它在30位和40位之间跳跃,我期望一个更稳定的值。是否有可能使噪音变小,使其在±1位上稳定?当然,外部电压参考将有帮助,我会尝试,但它不可能获得更多的稳定性与内部参考和没有过滤器?我正在使用:-分辨率:16位转换模式:2速率2000 SPS -输入模式:单缓冲器增益:1缓冲器模式:轨到轨-VREF:内部绕过P0.3-时钟:内部I代码:
空主(){初始();而(永远){AdCyStistCurror();AdcI ISEnTrimeAdvices(AdcWaWiTi FoRayREST);RAWDATA=ADCJGETRESULT32();SaMPTF(缓冲器,“%LD”,RAWDATA);UARTHIPPATSHIPE(缓冲器);UARTHIPPUCRLF(0x20);} 所以我把我的RAWDATA显示在我的终端上。谢谢 以上来自于百度翻译 以下为原文 Hi, i'm playing around with the ADC on the PSOC3, i've got the CY8CKIT-030. My Problem is even if i connect my input GPIO (P4.6) to VSSA, the rawvalue is very rough. It jumps around between bit 30 and bit 40, i expect a more stable value. Is it possible to get the noise smaller, so that it is stable on +-1 bit? Sure a external voltage reference will help, i will try that, but isnt it possible to get more stability with the internal reference and without a filter? I'm using: -resolution: 16 Bit -conversion mode: 2 -rate 2000sps -input mode: single -buffer gain: 1 -buffer mode: rail to rail -Vref: internal bypassed on P0.3 -clock: internal my code: void main() { Initial(); while(forever) { ADC_StartConvert(); ADC_IsEndConversion(ADC_WAIT_FOR_RESULT); Rawdata = ADC_GetResult32(); sprintf(Buffer, "%ld", Rawdata); UART_PutString (Buffer); UART_PutCRLF(0x20); } } so i get my rawdata displayed in my terminal. Thanks |
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如果你有一个高清晰度ADC,没有尽头的挑战得到
低噪声的结果,16位的2V参考是15的紫外线1/2 LSB。 首先通过使用无限持久性的范围来查看整体噪声, 看看电源轨和输入。这将给你的PK PK噪音你 正面临着。 这里是关于PSoC 3 ADC的AP注释 HTTP://www. CyPress?COM/?DOCID=30483 更多的参考资料,你想知道,附。 问候,Dana。 所有ATOD错误3.ZIP 12.1兆字节 以上来自于百度翻译 以下为原文 If you have a hi res adc there is no end to the challenges to getting low noise results, 16 bits with a 2V reference is 15 uV for 1/2 LSB. Start by looking at your overall noise by using scope on infinite persistance, and look at supply rails and inputs. That will give you the pk-pk noise you are facing. Here is an ap note on PSOC 3 ADC - http://www.cypress.com/?docID=30483 More reference material that you want to know, attached. Regards, Dana.
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如果你有一个高清晰度ADC,没有尽头的挑战得到
低噪声的结果,16位的2V参考是15的紫外线1/2 LSB。 首先通过使用无限持久性的范围来查看整体噪声, 看看电源轨和输入。这将给你的PK PK噪音你 正面临着。 这里是关于PSoC 3 ADC的AP注释 HTTP://www. CyPress?COM/?DOCID=30483 更多的参考资料,你想知道,附。 问候,Dana。 所有ATOD错误4.ZIP 12.1兆字节 以上来自于百度翻译 以下为原文 If you have a hi res adc there is no end to the challenges to getting low noise results, 16 bits with a 2V reference is 15 uV for 1/2 LSB. Start by looking at your overall noise by using scope on infinite persistance, and look at supply rails and inputs. That will give you the pk-pk noise you are facing. Here is an ap note on PSOC 3 ADC - http://www.cypress.com/?docID=30483 More reference material that you want to know, attached. Regards, Dana.
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一些额外的想法。
如果你看电源轨典型的200 mV的噪音,用30的紫外线。 LSB,即系统中的6700个LSB噪声。组件的PSRR可以帮助, 但是你可以看到一点噪音会使样品复杂化。 阅读样本。 尽可能使用差分测量,差分放大器的CMRR,ADC 前端,将有助于抑制和CM信号污染。在多个时钟上进行ADC的时钟 抽取器的响应频率,特别是零,这有助于CM噪声。 抑制。 看看你用来抑制噪音的帽子,聚合物是一种更美好的秩序。 Z(F)响应。陶瓷磁盘,实际上,看看数据表,不是所有的上限相等。 在它们的ESR曲线中。 问候,Dana。 以上来自于百度翻译 以下为原文 Some additional thoughts. If you look at power supply rail typical 200 mV+ of noise, with a 30 uV LSB, thats ~ 6700 l***s of noise in the system. PSRR of components can help, but you can see a little bit of noise goes a long way to complicating sample to sample readings. Use differential measurements whenever possible, the CMRR of the diff amp, ADC front end, will help with rejection and CM signal pollution. Clock the ADC at a multiple of the decimator response frequency, specifically the zeroes, that helps with CM noise suppression. Look at the caps you use to suppress noise, polymers an order of magniitude better Z(f) response. Ceramic disk as well, actually look at datasheets, not all caps are equal in their ESR curves. Regards, Dana. |
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你没有告诉我们在0号端口使用旁路盖(3),你连接了一个吗?
鲍勃 以上来自于百度翻译 以下为原文 You didn't tell about using a bypass cap at port 0(3) did you connect one? Bob |
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好的,谢谢-外部电压基准,基本上差模式帮助接近我的期望。我已经配置了一个外部旁路电容器。
现在值在-4bit和-7bit之间变化。下一步,我会尝试添加LP过滤器… 现在我很高兴-非常感谢! 以上来自于百度翻译 以下为原文 okay thanks - an external voltage reference and basically the difference mode helps to come close to my expectations. I had configured already an external bypass capacitor. Now the values varies between -4bit and -7bit. Next i will try to add a lp-filter... For now i'm happy - thanks a lot! |
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