[问答]

如何在S6中实现N-in MUX

1360 Mux

问答对人有帮助，内容完整，我也想知道答案 0 哦伟大的设计巫师！我想稍微挑选你的大脑。在S6中，使用ISE进行综合时，您对于描述N输入8位或16位组合多路复用器的建议是什么？有多种方法来实例化MUX，我猜测有一些编码风格可以比其他方法更好地合成资源使用或道具延迟。或许我错了，ISE中的综合工具非常聪明，无论使用何种编码风格，它都能产生最佳实现？嘿，谢谢（提前）你的建议！我认为这将是这些论坛中的常见问题解答主题，但搜索没有发现任何一般用途。（嗯....在这些支持论坛中有FAQ设施吗？）鲍勃埃尔金德（P.S.我住在Verilog的土地上，但我想这对VHDL爱好者来说也是普遍感兴趣的）签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。阅读手册或用户指南。你读过手册了吗？你能找到手册吗？2。搜索论坛（并搜索网页）以寻找类似的主题。不要在多个论坛上发布相同的问题。不要在别人的主题上发布新主题或问题，开始新的主题！5。学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。提供有用的详细信息（请与网页，数据表链接）.7。您的代码中的评论不需要支付额外费用。我没有支付论坛帖子的费用。如果我写一篇好文章，那么我一无所获。以上来自于谷歌翻译以下为原文 Oh great design wizards! I'd like to pick your brains for a bit. What are your recommendations for describing an N-input 8-bit or 16-bit combinatorial mux, in S6, using ISE for synthesis ? There are umpteen ways to instantiate MUXes, and I'm guessing that there are some coding styles which synthesize better than others for either resource usage or prop delay. Or maybe I'm wrong, and the synthesis tool in ISE is so darn clever that it can generate optimal implementations no matter what coding style is used ? Hey, thanks (in advance) for your suggestions! I figured this would be a FAQ topic in these forums, but a search didn't turn up anything of any general use. (Hmmm.... is there a FAQ facility in these support forums?) Bob Elkind (P.S. I live in Verilog land, but I imagine this is of general interest to VHDL lovers as well) SIGNATURE: README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369 Summary: 1. Read the manual or user guide. Have you read the manual? Can you find the manual? 2. Search the forums (and search the web) for similar topics. 3. Do not post the same question on multiple forums. 4. Do not post a new topic or question on someone else's thread, start a new thread! 5. Students: Copying code is not the same as learning to design. 6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please). 7. You are not charged extra fees for comments in your code. 8. I am not paid for forum posts. If I write a good post, then I have been good for nothing. 0
2019-5-27 11:44:37　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × asd008 该类别下有 32 个回答。邀请回答 aaaa321 该类别下有 27 个回答。邀请回答 doublelove 该类别下有 26 个回答。邀请回答 vynywrwr 该类别下有 21 个回答。邀请回答 hgjhgd 该类别下有 19 个回答。邀请回答 bwerwer 该类别下有 18 个回答。邀请回答 hanyan533 该类别下有 18 个回答。邀请回答 Jaionm 该类别下有 18 个回答。邀请回答 wang2222222 该类别下有 17 个回答。邀请回答 handsomelchcpp 该类别下有 17 个回答。邀请回答 binro 该类别下有 16 个回答。邀请回答 ningee 该类别下有 16 个回答。邀请回答 wznnzw 该类别下有 15 个回答。邀请回答 myf888 该类别下有 15 个回答。邀请回答 zcy615 该类别下有 14 个回答。邀请回答 wanglinhua2627 该类别下有 14 个回答。邀请回答 guotong1984 该类别下有 14 个回答。邀请回答 yhxc 该类别下有 14 个回答。邀请回答 armortech 该类别下有 14 个回答。邀请回答 60user25 该类别下有 14 个回答。邀请回答举报陈蕾相关推荐 • 请教给位大神这个电路怎么判断6个按键？另外两个按键同时按（例如S1，S6)能检测到吗？ 3925 • 如何用Spartan-6设计MIPI DSI接口？ 2910 • 2812或者28335PWM编程的问题 4307 • 如何在系统生成器中实现这种时钟多路复用器？ 1840 • 如何在功耗估算xl文件中包含virtex 6系列中的移动DDR io标准 788 • 如何在PSoC4100S Plus - CY8C4147AZI-S475中实现RTC？ 379 • Xilinx ISE工具和驱动程序未检测到Cmod怎么回事 1108 • AEC429-PCI-88/S6板卡调用动态链接库没有获取板卡句柄的函数 4833 • 请问将AD9513的OUT0和OUT1禁用该怎么设置S0~S10? 2239 • FFT如何在STM32中的实现与应用 1643 1个回答

答案对人有帮助，有参考价值 0 我通常使用case语句制作多路复用器，如果一切都符合时间，我就离开它在那。当N对于多路复用器而言太大而无法满足时序时，我喜欢创建流水线多级 mux，再次使用case语句。从理论上讲，综合工具可以搞清楚怎么做，但我并不总是愿意打开所有必需的旋钮（即注册重新定时等）。如果您的问题源于如何描述一般参数化的N输入在Verilog的mux，我还没有真正考虑过这一点。 Verilog有一些局限性因为定义描述二维结构的端口并不容易。它的很容易参数化输入的宽度，但输入的数量是另一个问题。您可能想在comp.lang.verilog上提出问题看看那里的大师们在想什么。你可能会从中获得大量的话语 Jonathan Bromley为什么需要VHDL来解决这个问题。祝你好运，的Gabor - Gabor 以上来自于谷歌翻译以下为原文 I generally make muxes with case statements and if everything meets timing I just leave it at that. When N gets too large for the mux to meet timing, I like to create a pipelined multistage mux, again using case statements. Theoretically the synthesis tools can figure out how to do this, but I'm not always willing to turn on all the required knobs (i.e. register retiming, etc.). If your problem stems from how to describe a general parameterized N-input mux in Verilog, I haven't really thought about that. Verilog has some limitations in that it isn't easy to define ports that describe a two-dimensional structure. It's easy enough to parameterize the width of the inputs, but the number of inputs is another issue. You may want to pose the question on comp.lang.verilog to see what the gurus there think. You're likely to get a large discourse from Jonathan Bromley on why you need VHDL for this. Good Luck, Gabor -- Gabor

2019-5-27 11:50:43 评论举报杨玲