所有IO引脚都拉了？

如果您的位文件未使用的I / O引脚设置为下拉，但您的引脚被拉高
它真的看起来部分没有正确配置。
DONE很奇怪
然而，光明来了。
除此之外，设备看起来就像它不会
已配置但配置期间的上拉有效（HSWAPEN或PUDC引脚上为低电平）。
好。
我只是看了你的原理图，看到问题......
DONE需要很高才能启动剩余的启动。
Q1保持不变
在大约.7V（Vbe on）完成，因此对FPGA的反馈看到DONE
永远保持低位。
您可以通过启用“内部”来解决此问题
在bitgen选项中“完成管道”。这允许FPGA在此基础上启动 
它的内部DONE信号而不是引脚反馈。
或者你可以从中拉出Q1
董事会并允许DONE走高。
使用外部的主要原因
DONE上的反馈是指您要配置多个部件
需要他们一起开始。
如果没有，内部DONE管道解决方案可以工作。
作为DONE信号上仍有LED的硬件解决方案，请添加
一个串联电阻到Q1的基极，比如3.3K欧姆。
或者用Q1替换Q1
逻辑电平N沟道FET。
问候，
的Gabor
-  Gabor



以下为原文

If your bit file has unused I/O pins set to pull down, but your pins are pulled high
it really looks like the part did not properly configure.  It is strange that the DONE
light comes on, though.  Other than that the device looks like it would if it were not
configured but pullup during config is active (low on HSWAPEN or PUDC pin).
 
O.K.  I just looked at your schematic and see the problem...
 
DONE needs to go high to enable the remainder of the startup.  Q1 is keeping
DONE at about .7V (Vbe on) so the feedback into the FPGA sees DONE
being kept low forever.  You can work around this by enabling the "internal
DONE pipe" in the bitgen options.  This allows the FPGA to start up based on
its internal DONE signal rather than pin feedback.  Or you can pull Q1 from
the board and allow DONE to go high.  The main reason to use the external
feedback on DONE is if you have more than one part to configure and you
need them to start up together.  If not, the internal DONE pipe solution could work.
As a hardware workaround to still have an LED on the DONE signal, either add
a series resistor to the base of Q1, say 3.3K ohms.  Or replace Q1 with
a logic-level N-channel FET.
 
Regards,
Gabor
-- Gabor

好抓，Gabor！
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
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不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
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以下为原文

Good catch, Gabor!
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