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免责声明:请耐心等待,因为我是新手。我也在搜索网(包括这个论坛),并没有找到解决我遇到的问题的方法。 我有一个带有64MB DDR ram(xc3s500e fg320 -4)的s3e套件,我想使用这个内存。 我正在运行ISE Webpack 10.1(并且考虑到我目前的连接 - 无法下载更新的版本)和MIG 2.1版。 我已经用MIG生成了大约21种不同的设计,但它们都没有工作(过去的2-1 / 2周)。 我已经尝试过参考板设计,但那些也没有用。 让我澄清一下:参考设计还包括一个位文件。 这在我的电路板上不起作用(没有一个led指示灯亮)。 所以我更改了UCF文件中的一些设置(例如将时钟设置为LOC C9等)并运行了ise_flow批处理脚本,我似乎遇到了很多约束错误。 我已经尝试过ISE的清理项目选项,但仍然没有用。 我尝试了MIG的新设计选项,并选择了0和3组来生成设计(也尝试了2和3)。 顺便说一句,在清理生成的代码之后(删除sys_clkb,将cntrl0_rst_dqs_div_in / out更改为cntrl0_rst_dqs_div,reset = active high等),此选项不会给我错误,我实际上能够生成一个位文件.Trace报告 我可以运行的最好的设计是78MHz(我假设我没有运行考虑这是我能做的最好的设计 - 虽然我不确定)。 另外,我认为运行SDRAM的最小值是77MHz。 我现在的设计(78MHz一个)运行时只点亮init_done,cntrl0_ddr_ras / cas_n和cntrl0_ddr_we_n led。 顺便说一下,我成功生成一个位文件的所有设计都表现出同样的行为。 cntrl0_led_error_output1和cntrl0_data_valid_out led都没有亮起。 所以我决定从顶层模块输出另外两个信号并将它们连接到示波器 - 这些信号是DCM生成的clk_0和clk90_0。 纳达! 示波器上没有活动 - 这意味着DCM不生成时钟。 我不知道为什么因为ucf文件将C9显示为具有LVCMOS25标准的“sys_clk”(可以吗?)并且该时钟被路由到IBUFG,IBUFG生成sys_clk_ibuf,而sys_clk_ibuf又连接到DCM作为输入。 NET“sys_clk”IOSTANDARD = LVCMOS25; NET“sys_clk”LOC =“C9”; #bank 0NET“sys_clk”PERIOD = 20.0ns HIGH 50%; 这整个过程非常令人沮丧,我希望有人在那里,做到了,并为我提供了解决方案。 我正在使用verilog(不熟悉VHDL)和这个整个HW的新东西(这是SW的一个受欢迎的硬件入口)。我和下一个人一样享受挑战,但这是令人讨厌的! 我不知道里面发生了什么,甚至不知道SDRAM是否被射击或.... 我知道我做错了但我不知道是什么(但是,我很惊讶Xilinx会发布一些不起作用的东西 - 来自软件,我不知道有人会怎么做 - 这当然导致我 相信我做错了什么)。 我欢迎任何事! 建议,提示,建议,侮辱,嘲笑 - 我只想让这个工作。 感谢阅读,如果可以的话,请帮忙。 缺口 以上来自于谷歌翻译 以下为原文 Hi all, Disclaimer: Please bear with me as I am new to this.I have also scoured the net (this forum included) and have not found a solution to the problems I'm having. I have a s3e kit with 64MB DDR ram (xc3s500e fg320 -4) and I would like to use this ram. I am running ISE Webpack 10.1 (and given the connection I have at the moment - its impossible to download a newer version) and MIG version 2.1. I have generated about 21 different designs with MIG but none of them are working (the past 2-1/2 weeks). I have tried the reference board designs and those haven't worked either. Let me clarify: The reference design also includes a bit file. This does not work on my board (none of the led's are on). So I changed a few settings in the UCF file (e.g setting the clock to LOC C9 etc) and ran the ise_flow batch script and I seem to get a lot of constraint errors. I've tried the cleanup project option from ISE but still, doesnt work. I tried the new design option from MIG and selected banks 0 and 3 to generate the design (also tried 2 and 3). Incidentally, after cleaning up the generated code a little bit (removing sys_clkb, changing cntrl0_rst_dqs_div_in/out to just cntrl0_rst_dqs_div, reset = active high etc) this option does not give me the errors and I am actually able to generate a bit file.Trace reports the best I can run the design is 78MHz (which I'm assuming Im not running at considering this is the best I can do given the design - I dont know for sure though). Plus, I think the minimum I can run the SDRAM is 77MHz. The design I have now (the 78MHz one) when run only lights up the init_done, cntrl0_ddr_ras/cas_n and cntrl0_ddr_we_n led. BTW, all the designs I've successfully generated a bit file for exhibit this very same behavior. Neither the cntrl0_led_error_output1 nor the cntrl0_data_valid_out led's are lit up. So I decided to output two more signals from the top level module and connected them to an oscilloscope - these signals are the clk_0 and clk90_0 generated by the DCM. Nada!! There is no activity on the oscilloscope - which means the DCM is not generating the clocks. I have no idea why since the ucf file shows C9 as my "sys_clk" with a standard of LVCMOS25 (Is that okay?) and that clock is routed to a IBUFG which generates sys_clk_ibuf which in turn is connected to the DCM as an input. NET "sys_clk" IOSTANDARD = LVCMOS25; NET "sys_clk" LOC = "C9" ; #bank 0 NET "sys_clk" PERIOD = 20.0ns HIGH 50%; This whole experience is extremely frustrating and I'm hoping that someone has been there, done that and has a solution for me. I am using verilog (not familiar with VHDL) and pretty new to this whole HW thing (what a welcome entry to HW from SW).I enjoy a challenge as much as the next guy but this is bewidlering! I dont know what is going on inside there and dont even know if the SDRAM is shot or not or .... I know I'm doing something very wrong but I dont know what (however, I'm pretty surprised that Xilinx would release something that does not work - coming from software, I dont know how anyone would do that - which of course leads me to believe that I am doing something wrong). I welcome anything! Suggestions, tips, advice, insults, ridicules - I would just like to get this to work. Thanks for reading and if you can, please help. Nick |
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23个回答
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因为听起来你有很多问题,所以从非常简单的事情开始。
路线 一个简单的计数器输出引脚并验证它们是否有效: reg [3:0] cnt ='b0; 总是(posedge clk) CNT 看看这是否可以让你开始。 约翰普罗塞纳 以上来自于谷歌翻译 以下为原文 Since it sounds like you are having multiple problems, start with something very simple. Route a simple counter to output pins and verify that they work: reg [3:0] cnt = 'b0; always (posedge clk) cnt <= cnt + 1'b1; You should be able to hook something like this up and verify that you can synthesize & download a design to the board. Next, try adding the DCM to buffer the clock. Make sure you bring out the DCM lock signal to a pin so you can make sure that the DCM achieves lock. You should probably feed a power-reset to the DCM, something simple like this will work: reg [15:0] rst_pipe = 'b0; always @(posedge clk) rst_pipe <= {rst_pipe, 1'b1}; wire power_rst = ~rst_pipe[15]; Make sure you don't use the clock from the DCM to drive the power-on-reset! You must use the clock from the pads! See if this gets you started. John Providenza |
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你好,约翰,
感谢您及时的回复。 我已经能够合成其他电路,并实际上让它们在该板上工作。 为了仔细检查,我使用DCM(用于驱动LCD)生成了9MHz时钟,它的工作效果非常好。 所以我知道董事会应该没问题。 我不明白为什么它仍然不起作用。 缺口 以上来自于谷歌翻译 以下为原文 Hi John, Thanks for the quick response. I have been able to synthesize other circuits and actually get them to work on that board. Just to double check, I generated a 9MHz clock using a DCM (for driving an LCD) and it works just great. So I know that the board should be fine. I dont understand why it still does not work. Nick |
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好的...所以我刚刚更新到ISE 10.1SP3,其中包括MIG 2.3,并尝试简单地为spartan 3e生成参考板ddr控制器。
ReadMe文件声称使用板载时钟以133MHz成功运行测试。 但是,它附带的位文件不起作用。 没有一个LED甚至点亮。 Xilinx是否甚至在一个简单的3e套件上测试它? 说真的,任何人 - 更不用说一个公司,如何运出那些不起作用并声称它的东西? 很明显,我没有参与位文件的生成 - 这意味着它不是用户错误。 我创造了一个新的设计,没有led的照明。 有人有这个工作吗? 这怎么可能? 以上来自于谷歌翻译 以下为原文 Okay...so I just updated to the ISE 10.1SP3 which among other things includes MIG 2.3, and tried to simply generate the reference board ddr controller for spartan 3e. The ReadMe file claims that the test was successfully run at 133MHz using the on board clock. BUT, the bit file that comes with it DOES NOT work. None of the leds even light up. Did Xilinx even test it on a spartan 3e kit at all? Seriously, how does anyone - let alone a corporation, ship out stuff that does NOT WORK and claim it does? Clearly, I had no hand in the generation of the bit file - so that means its not a user error. I generated a new design and no led's light up. Has anyone got this to work at all? How is this possible? |
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听起来有一些基本问题正在发生。
你绝对相信MIG的refence设计针对你正在使用的确切板吗? 您的电路板是否有损坏或FPGA已损坏? 您是否查看过Xilinx的答复记录,看看是否存在任何已知问题? 约翰普罗塞纳 以上来自于谷歌翻译 以下为原文 It sounds like there is some fundamental problem going on. Are you absolutely sure that the refence design from MIG targets the exact board that you're using? Any chance your board has been damaged or the FPGA has been damaged? Have you checked Xilinx' answer records to see if there is any known issues? John Providenza |
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我已经使用MIG生成了许多设计,我确信参考设计与我的电路板相匹配。
斯巴达3e xc3s500e-FGG320 -4。 在生成设计时,我选择spartan 3e,fg320,-4,选择Verilog作为HDL和ISE进行合成。 在下一页,斯巴达板有4种选择,但只有一种用于斯巴达3e套件,这就是我所拥有的。 我还使用这个相同的FPGA套件设计了许多其他电路,它们运行良好。 最重要的是,我从来没有删除它附带的ROM程序,所以在加电时,它会在LCD xter显示屏上显示文本。 以上来自于谷歌翻译 以下为原文 I have generated numerous designs with MIG and I am sure the reference designs match my board. A spartan 3e xc3s500e-FGG320 -4. In generating the design, I choose spartan 3e, fg320, -4, select Verilog as the HDL and ISE for synthesis. On the next page, there are 4 choices for a spartan board but only one for a spartan 3e kit, which is what I have. I have also designed many other circuits using this very same FPGA kit and they work well. On top of that, I never erased the ROM program it comes with so on power up, it displays the text on the LCD xter display. |
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嗨,
我知道软件V硬件的挑战,我不得不反过来对你这么做,我不能相信与ASM相比产生的代码的长篇大论,但这是另一个我们不会进入的故事 这里..... 无论如何。 请问澄清一下。 你有一个工作项目的董事会,你写的一个或董事会附带的项目。 也就是说它会像你期望的那样闪烁灯光。 我的困惑是电路板附带的位文件应该“开箱即用”。 我也很困惑,因为你编辑了随板提供的ucf文件以使其工作。 这不应该是必须的。 为了强化早期的响应之一,我发现硬件是否正在做“奇怪”的事情,然后它引起了它的奇怪之处! 我会退后一步,喝几杯咖啡/新的一天,专注于参考板设计。 你知道代码是有效的,所以这是一个不用担心的变量。 回到已知的干净参考设计,因为您将从SW背景中了解版本控制等的重要性。 将参考位文件下载到电路板(不要重新编译它或任何东西),并确认这样做符合您的预期。 如果是,请尝试重新编译和下载并确认它仍然按预期执行。 如果位文件不起作用,要么你没有你认为的文件/板,要么板/程序员'怀疑'。 我已经完成了,可能代码实际上没有被下载到电路板上,但是它仍然从板载PROM中出现。 尝试使用JTAG擦除板载舞会。 还有一件事需要澄清,那就是电路板开箱即用? 我问,因为这些板上有许多正常的配置选项,尤其是FPGA的时钟来自/去往的地方。 希望这会有所帮助,并让我们了解你如何继续前进。 你永远不会知道我可能会问你一两个问题。 以上来自于谷歌翻译 以下为原文 Hi, I know about the challenge of software V hardware, I'm having to do it the other way around to you, and I can not believe the long windedness of the code generated compared to ASM, but that's another story which we WILL NOT get into here..... Anyway. can I ask for a clarification please. Have you a working project for the board, either one that you wrote or one that came with the board. i.e. it flashes the lights etc as you'd expect it to. My confusion is the bit file that came with the board should have worked 'out the box'. I'm also confused in that you edited the ucf file that came with the board to make it work. Again this should not have been required. To reinforce one of the earlier response, I find if the hardware is doing 'strange' things, then it's something strange that has caused it ! I'd take big step back, a few cups of coffee / a new day and concentrate on the reference board designs. You know the code works, so that is one less variable to worry about. Go back to the known clean reference designs, as your from the SW background you'll know all about the importance of version control etc. Download the reference bit file to the board ( don't re compile it or anything ), and confirm that does as you expect. If it does , then try re compiling and downloading and confirm it still does as you expect. If the bit file did not work, either you do not have the file / board you think you have, or the board / programmer is 'suspect'. I've done it, it's just possible that the code is not actual being downloaded to the board, but it keeps coming up from the on board PROM. Try with the JTAG to erase the on board prom. One other thing to clarify, is the board as it came out of the box ? I ask as there are normal a number of configuration options on these boards, not least where the clock to the FPGA is coming from / going to. Hope this helps and keep us in the loop as to how yo get on. You never know I might ask you an OO question or two. |
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嗨drjohnsmith,
这就是问题,位文件 MIG生成的(即当我选择参考时产生的一个MIG) 电路板设计 - 没有来自我的输入)不能立即使用。 一世 已经尝试了很多次(每一个新的参考设计 生成)。我加载它而不是单个LED灯亮起来。所以我生成了一个 非参考设计,因为我似乎有这样的运气 (至少有些领导者亮了)。 我编程了 董事会多次,设计工作得很好。 董事会 选项,实际上只有一个地方(斯巴达3e套件)。 这样就证实了程序员的工作原理以及董事会的工作原理。 更新: 所以我运行了MIG(非参考设计),相应地调整了UCF文件 (现在大约2周内第一次),不仅是ras,cas 和init_done领导,但data_valid_out和错误指令也是如此。 显然我喜欢错误导致但是嘿,你必须先爬行 你走。 这是董事会生活中一个受欢迎的标志。设计是 能够以81.593MHz的速度运行(至少跟踪它的情况)。 现在 下一个问题是它失败的原因以及如何摆脱错误。 但 男人,我告诉你,只是看着领导(即使错误导致)正在制作 我的一天。 我不认为它会有助于附加 iseflow_results和ucf文件没有设计,但以防万一 一直在那里,我正在附上它们。 真的,感谢所有人 建议伙计们。 ise_flow_results.txt 164 KB 以上来自于谷歌翻译 以下为原文 Hi drjohnsmith, Thats just the problem, the bit filethat MIG generates (i.e the one MIG generates when I select a referenceboard design - no input from me) does not work right out of the box. Ihave tried that numerous times (with every new reference designgenerated).I load it and not a single led lights up.So I generate anon-reference design since I seem to have a little more luck this way(at least some led's light up). I have programmed theboard many times and the designs work just fine. As far as the boardoptions, there is really only one where it counts (the spartan 3e kit).So that confirms that the programmer works and so does the board. Update:So I ran MIG (non-ref design), tweaked the UCF file accordingly and now(for the first time in about 2 weeks now), not only are the ras, casand init_done led's on but so are the data_valid_out and error leds.Obviously I'd like the error led off but hey, you gotta crawl beforeyou walk. That is a welcome sign of life on the board.The design iscapable of running at 81.593MHz (at least as trace sees it). Now thenext question is why its failing and how to get rid of the errors. Butman I tell you, just watching the led's (even the error led) is makingmy day. I dont suppose it would help just attaching theiseflow_results and ucf files w/out the design but just in case someonehas been there, I'm attaching them. Really, thanks for all thesuggestions guys. |
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我无法附加这两个文件(对我不好),所以这里是UCF文件。
我希望我没有提交多个帖子。 mine.ucf 45 KB 以上来自于谷歌翻译 以下为原文 I was not able to attach both files (kept erring on me) so here is the UCF file. I hope I didn't submit multiple posts. |
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你好
当你说董事会的拒绝设计不起作用时,我有点失意。 当我从Xilinx获得一块电路板时,它附带一块CD,其中包含一块或两块用于该电路板的设计,可以下载并证明电路板。 无需运行MIG,只需编程工具。 你有那张CD吗?你可以在那张CD上安装这个位文件,然后按照CD上的文档中的说明操作电路板吗? 以上来自于谷歌翻译 以下为原文 Hi I'm a little concered when you say the referance design with the board does not work. When I get a board from Xilinx, it comes with a cd containing a design or two for that board, which can just be downloaded and proves the board. No need to run MIG , just the programming tools. Have you that CD, and can you install the bit file on that CD and does the board then work as described in the documentation on the CD ? |
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我不确定为什么为Spartan-3E入门套件提供的MIG参考设计不适合您。
它应该,虽然我承认我最近没有尝试过。 我知道你不能为XC3S500E生成一个全新的设计,更改S3E Starter的UCF,并使其工作。 查看S3E参考设计中readme.txt的注释: “对于在Spartan-3E入门套件板上定位的核心所需的rtl和模拟文件有几处手动修改。要查看所有这些更改,请在所有rtl和sim文件中搜索包含”SPARTAN-的注释行“ 3E STARTER KIT“。 这些变化包括: 1.环回信号是使用单个IO引脚完成的,而不是输出引脚,板上的环路,返回输入 销。 因此,网络cntrl0_rst_dqs_div_in和cntrl0_rst_dqs_div_out已折叠为单网称为 cntrl0_rst_dqs_div。 信号通过输出缓冲器简单地循环,然后通过相同的引脚输入返回 缓冲。 实际的电路板环回长度通常是控制器正常运行的关键指标, 环回设计不是在这个板上设计的。 为了减轻这种影响,延迟时间到/来自 必须考虑cntrl0_rst_dqs_div引脚,并且必须稍微修改data_read_controller。 2. net control0_rst_dqs_div应放在数据库的中心。 而是在Spartan-3E入门套件中放置此信号 在不同的银行中,因此该信号的延迟超过预期的延迟。 周围可能还有MAXDELAY违规行为 在这个网上1.6ns。 为了克服这个问题,在data_read_controller中为rst_dqs_div信号选择的LUT数量减少了 对数据。 3.参数文件中的reset_active_low参数更改为1'b0,以使用电路板的高电平瞬时按钮。 4.将cntrl0_led_error_output1带到LD0,并将cntrl0_data_valid_out带到板上的LD1。 数据比较 如果LD1被轻微照射(循环脉冲信号),则仅认为测试台没有错误,而LD0不是 照亮。 Spartan-3E引脚分配应考虑以下规则。 1.奇数编号的DQ位应分配给一个磁贴的顶部焊盘,偶数编号的DQ位应分配给 IO瓦的底垫.. 2.没有两个偶数DQ位或没有两个奇数DQ位应连接到同一IO区块。 由于SPARTAN-3E STARTER KIT的某些引脚未遵循上述规则,因此我们修改了由mig生成的rtl以适应Starter Kit硬件。 添加了一个新模块ram8d_1,手动修改了ram8d_0模块。“ 出于同样的原因,如果您使用Spartan-3E和DDR设计自己的电路板,则不应遵循S3E入门工具包上的引脚分配。 您应该从最新的MIG生成一个全新的设计,并使用它给你的引脚分配。 可以修改引脚排列并保持在MIG规则的范围内,但您需要了解规则。 布赖恩 以上来自于谷歌翻译 以下为原文 I'm not sure why the provided MIG reference design for the Spartan-3E Starter Kit isn't working for you. It should, although I will admit that I haven't tried it myself recently. I do know that you cannot generate a brand-new design for a XC3S500E, change the UCF for the S3E Starter, and get it to work. Check out the notes from the readme.txt from the S3E reference design: "There were several hand-modifications to the rtl and simulation files required to do to the core targetted on the Spartan-3E Starter Kit board. To view all of these changes, search all rtl and sim files for comment lines that contain "SPARTAN-3E STARTER KIT". These changes include: 1. The loop-back signal is being done using a single IO pin, rather than an output pin, a loop on the board, back into an input pin. Therefore, the nets cntrl0_rst_dqs_div_in and cntrl0_rst_dqs_div_out have been collapsed to single net known as cntrl0_rst_dqs_div. The signal simply loops out through an output buffer, and then back in through the same pin's input buffer. While the actual board loopback length is normally a critical measurement for proper operation of the controller, the loopback was not designed on this board. To mitigate for the effects of this, the delay time to/from the cntrl0_rst_dqs_div pin had to be taken into account, and the data_read_controller had to be very slightly modified. 2. The net control0_rst_dqs_div should be placed in the center of the data bank. Instead in Spartan-3E starter kit this signal placed in different bank, As a result the delay on this signal is more than the expected delay. There may also be MAXDELAY violation of around 1.6ns on this net. To overcome this issue number of LUTs selected for rst_dqs_div signal in data_read_controller is reduced compared to the data. 3. reset_active_low parameter in parameter file is changed to 1'b0 to use the board's active-high momentary pushbuttons. 4. cntrl0_led_error_output1 is brought to LD0, and cntrl0_data_valid_out is brought to LD1 on the board. The data comparison in the testbench is only considered to be error-free if LD1 is lightly illuminated (cyclical pulse signal), while LD0 is not illuminated. Spartan-3E pin allocation should consider the following rule. 1. Odd numbered DQ bit should be allocated to the top pad of an tile and even numbered DQ bits should be allocated to the bottom pad of an IO tile.. 2. No two even DQ bits or no two odd DQ bits should be connected to the same IO tile. As some of the pins of the SPARTAN-3E STARTER KIT not followed the above rule, we modified the rtl generated out of mig to suit the Starter Kit hardware. A new module ram8d_1 is added and ram8d_0 module was hand modified." It is for these same reasons that if you are designing your own board with Spartan-3E and DDR, you should not follow the pinout on the S3E Starter Kit. You should generate a fresh design from the latest MIG and use the pinout that it gives you. It is possible to modify the pinout and stay within the bounds of the MIG rules, but you need to understand the rules. Bryan |
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啊,我明白你的意思了......好吧,我从Digilent(www.digilentinc.com)购买了这块板,由于许可问题,他们无法提供*任何* Xilinx相关的文档或软件。
我刚买了一块带编程电缆的电路板,就是这样。 所以我没有任何测试代码或者我可以回复的任何类型的测试代码来测试电路板。 但是,我已经为它写了一些测试,并且电路板似乎工作得很好。 我假设你有一个类似的板,你已经设法让DDR工作。 如果是这样,请您分享您对如何做的见解? 我会很感激 - 我应该说,DDR设计正在运行但是导致的错误一直在持续,我还没有设法让它通过。 DDR是如此痛苦 - 但没有它,我的项目是无用的。 谢谢! 以上来自于谷歌翻译 以下为原文 Ah I see what you mean..Well, I bought this board from Digilent (www.digilentinc.com) and due to licensing issues, they are unable to provide *any* Xilinx related documentation or software. I just got a board with the programming cables and that was it. So I dont have any test code for it or anything of the sort that I can revert to, to test the board. However, I have written a few tests for it and the board seems to work quite well. I am assuming that you have a similar board and that you have managed to get the DDR to work. If so, would you please share your insights on how you did it? I would appreciate it - I should say, the DDR design is running but the error led is constantly on and I have not managed to get it to pass. The DDR is such a pain - but without it, my project is useless. Thanks! |
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嗨布莱恩,
我不确定为什么为Spartan-3E提供MIG参考设计 入门套件不适合您。 应该,虽然我会承认 我最近自己没有尝试过。 我不知道为什么它对我也不起作用。 有一个自述文件意味着它打算与chipcope一起使用? 我没有 - 但即便如此,生成的设计使用引脚A10作为时钟,我相信是用户提供的外部时钟。 除了将sys_clk更改为C9之外,我还没有看到MIG生成的参考板设计还有哪些变化。 它根本不起作用。 领导者甚至没有点亮。 在这个阶段我不认为我做错了 - 这是序列 1.生成Spartan 3E入门套件设计 2.导航到位文件所在的文件夹 3.更改UCF文件以使用C9作为sys_clk而不是A10 4.运行ise_flow.bat以生成新的位文件 这里有很多错误.. 我知道你不能为XC3S500E生成一个全新的设计,更改S3E Starter的UCF,并使其工作。 我拥有一个Spartan 3E入门套件,因此应该可以立即使用。 但是,由于它没有,我正在生成一个新设计,并在新设计中进行这些更改。 但是,我知道我没有在这里做某事,因为即使生成了一个位文件,设计也会失败并且运行速度比参考设计应该运行的速度慢很多(133MHz) 可以修改引脚排列并保持在MIG规则的范围内,但您需要了解规则。 是的 - 非常真实。 我*不*理解规则 - 我一直在阅读Xilinx文档,所以我慢慢到那里。 以上来自于谷歌翻译 以下为原文 Hi Bryan, I'm not sure why the provided MIG reference design for the Spartan-3EStarter Kit isn't working for you. It should, although I will admitthat I haven't tried it myself recently. I am not sure why it does not work for me either. There is a readme file that implies that it is intended to be used with chipscope? Which I dont have - but even then, the generated design uses pin A10 for the clock which I believe is for the user supplied external clock. Besides changing the sys_clk to C9, I dont see what else to change from the MIG generated reference board design. It is simply not working. The led's do not even light up. I don't think I'm doing anything wrong at this stage - here is the sequence 1. Generate a Spartan 3E starter kit design 2. Navigate to the folder where the bit file is located 3. Change the UCF file to use C9 as the sys_clk as opposed to A10 4. Run ise_flow.bat to generate a new bit file 5. A lot of errors here.. I do know that you cannot generate a brand-new design for a XC3S500E, change the UCF for the S3E Starter, and get it to work. I own a Spartan 3E Starter Kit so that should work right out the box. But since it does not, I am generating a new design and making those changes in that new design. However, I know that I'm not doing something right here because even though a bit file is generated, the design fails and is running a lot slower than what the reference design should run at (133MHz) It is possible to modify the pinout and stay within the bounds of the MIG rules, but you need to understand the rules. Yeah - very true. I do *not* understand the rules- ive been reading up on Xilinx docs so I'm slowly getting there. |
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你好
没见过Digilent的东西,所以看了看。 我可以理解为什么他们不允许提供任何Xilinx的东西,但他们确实在网站上提供了referance设计。 http://www.digilentinc.com/Support/Support.cfm?NavTop=85 我不知道你有哪个电路板,但是我会从电路板设计师的设计开始,然后继续修改它以达到你想去的地方。 试图从错误的电路板工作中获得设计将是“有趣的”。 从一个有效的开始始终是一个很好的捷径。 以上来自于谷歌翻译 以下为原文 Hi not seen the Digilent stuff, so had a look. I can understand whythey are not allowed to supply any Xilinx stuff, but they do supply referance designs on the site. http://www.digilentinc.com/Support/Support.cfm?NavTop=85 I don't know which board you have, but I'd start withthe referance design from the board designers, then step on modifying that to get to where you want to go. Trying to get a design from the wrong board working is going to be 'fun'. Start with one that works is always a good short cut. |
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你好,约翰,
如果我下载这些设计并用它们编程我的fpga,它只会证明我可以配置fpga并且电路板工作正常。 好吧,我已经做到了。 我有可以加载/配置fpga的设计,它们运行没有任何问题 - 所以这部分是照顾的。 我的问题是DDR SDRAM。 现在,它失败了,我认为它与dq *组件的放置有很大关系(奇数在顶部瓷砖上,甚至在底部瓷砖上编号 - 无论这意味着什么)。 我将生成新设计时生成的ucf文件与选择自定义板(spartan 3e套件)时生成的ucf文件进行了比较,并对时钟和循环时钟进行了调整。 我注意到在这些更改之后,设计正在运行(但失败)。 但是,我没有改变dq *组件 - 因为我不知道我在做什么。 任何人都可以对此有所了解(PS:我不能复制并粘贴这些更改,因为我正在生成的设计中为我的LCD保留了一些引脚)。 有没有讨论这个东西的文件? 即瓷砖。 我希望它失败的原因是因为dq *位的错位。 非常感谢! 缺口../ 以上来自于谷歌翻译 以下为原文 Hi John, If I download these designs and program my fpga with them, it will only prove that I can configure the fpga and that the board is working correctly. Well, I have already done that. I have designs that I can load/configure the fpga with and they run without any problems - so that part is taken care of. My problem is with the DDR SDRAM. Right now, its failing and I think that it has a lot to do with the placement of the dq* components (odd numbered on top tiles and even numbered on bottom tiles - whatever that means). I compared the ucf file generated when I generate a new design to the one generated when I select the custom board (spartan 3e kit) and made adjustments to the clock and the loop back clock. I noticed that after these changes, the design is running (but failing). However, I have not changed the dq* components - because I dont know what I am doing. Can anyone please shed some light on this (PS: I just cant copy and paste these changes since some pins are reserved for my LCD in the design I'm generating). Is there any document that discusses this stuff? i.e the tiles. I'm hoping that the reason its failing is because of the misplacement of the dq* bits. Thanks a lot! Nick../ |
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你好
向演示板制造商提出设计的原因部分是为了证明电路板,但主要是为了“借用”设计。 我假设他们的参考设计有DDR驱动,并有一个UCF文件。 所以我先从他们的工作设计开始,然后根据你的需要进行修改,然后进行测试。 这是FPGA的优势之一,你可以在真正的硅片中采取小步骤和“模拟”,而不像你必须模拟死亡的ASICS。 还应该有一些来自电路板制造商的应用笔记,说明他们如何使DDR工作,以及他们必须手工实现的任何功能。 以上来自于谷歌翻译 以下为原文 Hi the reason for suggesting the designs from the demo board manufacturer was partly to prove the boards, but mainly for you to 'borrow' the design. I assume their reference design has DDR driven, and has a UCF file. So I'd start with their working design and modify it to what you want, testing as I go. That's one of the advantages of FPGA's, you can take small steps and 'simulate' in real silicon, not like ASICS where you have to simulate to death. There should also be some app notes from the board manufacturer as to how they got the DDR working, and any features they had to hand implement. |
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啊,我看到......好吧,他们似乎没有DDR参考设计(我希望他们这样做)。
它们只有一些基本模块,但没有DDR。 只是我的运气! 谢谢 以上来自于谷歌翻译 以下为原文 Ah I see...well, they dont seem to have a DDR reference design (I wish they did). They only have a few basic modules but not DDR. Just my luck! Thanks |
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你好
所以你有一块主板,上面有DDR ram,但是这个参考板的制造商没有DDR的评估代码? 惊人。 我将与演示板供应商进行长时间的聊天,了解代码的位置以及他们如何使DDR工作。 我还强烈建议你买一个Xilinx演示板,它上面有DDR工作示例。 以上来自于谷歌翻译 以下为原文 Hi So you have a board, with DDR ram on it, but the manufacturer of this ref board has no evaluation code for the DDR ? Amazing. I'd have a long chat with the demo board supplier as to where the code is and how they got the DDR to work. I'd also strongly suggest you get a Xilinx demo board, which has working DDR examples on it. |
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你好,约翰,
但它与Xilinx提供的功能相同。 我甚至查阅了规格,它与Xilinx提供的电路板完全相同。 事实上,在Xilinx网站(http://www.xilinx.com/products/devkits/HW-SPAR3E-SK-US-G.htm)上 - 这就是我所拥有的。 最初,当我买下它时,我根据学术选项查找了董事会,所列出的董事会由Digilent出售。 缺口../ 以上来自于谷歌翻译 以下为原文 Hi John, But its the same board as Xilinx offers. I even looked up the specs and it is exactly the same board that Xilinx offers. In fact, on the Xilinx website (http://www.xilinx.com/products/devkits/HW-SPAR3E-SK-US-G.htm) - it is what I have. Initially when I bought it, I had looked up boards under the academic option and the board listed was sold by Digilent. Nick../ |
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你好
这是一个很好的发现。 在这种情况下,您可以访问工作的Xilinx演示代码。 只需下载它,并把它放在板上。 完成后,尝试将代码修改为您想要的内容,一次一步。 以上来自于谷歌翻译 以下为原文 Hi that is a good find. In that case, you have access to the working Xilinx demo code. just download it, and put it on the board. Once that is done, then try modifying the code to what you want, one step at a time. |
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