斯巴达3E上的DDR Ram不起作用

大家好，
免责声明：请耐心等待，因为我是新手。我也在搜索网（包括这个论坛），并没有找到解决我遇到的问题的方法。
我有一个带有64MB DDR ram（xc3s500e fg320 -4）的s3e套件，我想使用这个内存。
我正在运行ISE Webpack 10.1（并且考虑到我目前的连接 - 无法下载更新的版本）和MIG 2.1版。
我已经用MIG生成了大约21种不同的设计，但它们都没有工作（过去的2-1 / 2周）。
我已经尝试过参考板设计，但那些也没有用。
让我澄清一下：参考设计还包括一个位文件。
这在我的电路板上不起作用（没有一个led指示灯亮）。
所以我更改了UCF文件中的一些设置（例如将时钟设置为LOC C9等）并运行了ise_flow批处理脚本，我似乎遇到了很多约束错误。
我已经尝试过ISE的清理项目选项，但仍然没有用。
我尝试了MIG的新设计选项，并选择了0和3组来生成设计（也尝试了2和3）。
顺便说一句，在清理生成的代码之后（删除sys_clkb，将cntrl0_rst_dqs_div_in / out更改为cntrl0_rst_dqs_div，reset = active high等），此选项不会给我错误，我实际上能够生成一个位文件.Trace报告
我可以运行的最好的设计是78MHz（我假设我没有运行考虑这是我能做的最好的设计 - 虽然我不确定）。
另外，我认为运行SDRAM的最小值是77MHz。
我现在的设计（78MHz一个）运行时只点亮init_done，cntrl0_ddr_ras / cas_n和cntrl0_ddr_we_n led。
顺便说一下，我成功生成一个位文件的所有设计都表现出同样的行为。
cntrl0_led_error_output1和cntrl0_data_valid_out led都没有亮起。
所以我决定从顶层模块输出另外两个信号并将它们连接到示波器 - 这些信号是DCM生成的clk_0和clk90_0。
纳达！
示波器上没有活动 - 这意味着DCM不生成时钟。
我不知道为什么因为ucf文件将C9显示为具有LVCMOS25标准的“sys_clk”（可以吗？）并且该时钟被路由到IBUFG，IBUFG生成sys_clk_ibuf，而sys_clk_ibuf又连接到DCM作为输入。
NET“sys_clk”IOSTANDARD = LVCMOS25;
NET“sys_clk”LOC =“C9”;
#bank 0NET“sys_clk”PERIOD = 20.0ns HIGH 50％;
这整个过程非常令人沮丧，我希望有人在那里，做到了，并为我提供了解决方案。
我正在使用verilog（不熟悉VHDL）和这个整个HW的新东西（这是SW的一个受欢迎的硬件入口）。我和下一个人一样享受挑战，但这是令人讨厌的！
我不知道里面发生了什么，甚至不知道SDRAM是否被射击或....
我知道我做错了但我不知道是什么（但是，我很惊讶Xilinx会发布一些不起作用的东西 - 来自软件，我不知道有人会怎么做 - 这当然导致我
相信我做错了什么）。
我欢迎任何事！
建议，提示，建议，侮辱，嘲笑 - 我只想让这个工作。
感谢阅读，如果可以的话，请帮忙。
缺口



以下为原文

Hi all,

Disclaimer: Please bear with me as I am new to this.I have also scoured the net (this forum included) and have not found a solution to the problems I'm having.

I have a s3e kit  with 64MB DDR ram (xc3s500e fg320 -4) and I would like to use this ram. I am running ISE Webpack 10.1 (and given the connection I have at the moment - its impossible to download a newer version) and MIG version 2.1. I have generated about 21 different designs with MIG but none of them are working (the past 2-1/2 weeks). I have tried the reference board designs and those haven't worked either. Let me clarify: The reference design also includes a bit file. This does not work on my board (none of the led's are on). So I changed a few settings in the UCF file (e.g setting the clock to LOC C9 etc) and ran the ise_flow batch script and I seem to get a lot of constraint errors. I've tried the cleanup project option from ISE but still, doesnt work.

I tried the new design option from MIG and selected banks 0 and 3 to generate the design (also tried 2 and 3). Incidentally, after cleaning up the generated code a little bit (removing sys_clkb, changing cntrl0_rst_dqs_div_in/out to just cntrl0_rst_dqs_div, reset = active high etc) this option does not give me the errors and I am actually able to generate a bit file.Trace reports the best I can run the design is 78MHz (which I'm assuming Im not running at considering this is the best I can do given the design - I dont know for sure though). Plus, I think the minimum I can run the SDRAM is 77MHz.

The design I have now (the 78MHz one) when run only lights up the init_done, cntrl0_ddr_ras/cas_n and cntrl0_ddr_we_n led. BTW, all the designs I've successfully generated a bit file for exhibit this very same behavior. Neither the cntrl0_led_error_output1 nor the cntrl0_data_valid_out led's are lit up. So I decided to output two more signals from the top level module and connected them to an oscilloscope - these signals are the clk_0 and clk90_0 generated by the DCM. Nada!! There is no activity on the oscilloscope - which means the DCM is not generating the clocks. I have no idea why since the ucf file shows C9 as my "sys_clk" with a standard of LVCMOS25 (Is that okay?) and that clock is routed to a IBUFG which generates sys_clk_ibuf which in turn is connected to the DCM as an input.

NET  "sys_clk"                                  IOSTANDARD = LVCMOS25;
NET  "sys_clk"                                    LOC = "C9" ;     #bank 0
NET "sys_clk" PERIOD = 20.0ns HIGH 50%;


This whole experience is extremely frustrating and I'm hoping that someone has been there, done that and has a solution for me. I am using verilog (not familiar with VHDL) and pretty new to this whole HW thing (what a welcome entry to HW from SW).I enjoy a challenge as much as the next guy but this is bewidlering! I dont know what is going on inside there and dont even know if the SDRAM is shot or not or ....

I know I'm doing something very wrong but I dont know what (however, I'm pretty surprised that Xilinx would release something that does not work - coming from software, I dont know how anyone would do that - which of course leads me to believe that I am doing something wrong). I welcome anything! Suggestions, tips, advice, insults, ridicules -  I would just like to get this to work. Thanks for reading and if you can, please help.

Nick