FX3布局造成了相当大的19MIL 50欧姆单端痕迹

请忽略图片中显示的错误，从ESD设备到电容器的路由没有正确间隔。



     以下为原文
   Please ignore my mistake shown in the picture, the routing from the ESD device to the capacitors is not spaced correctly. 

在花了一些时间阅读这件事之后，我开始回答我自己的问题：
1）我认为有两个主要原因，为什么使用12/8 / 12欧姆差分边缘耦合微带。这些都与损失和公差有关。由于在~5GHz USB发送/接收频率的趋肤效应，更宽的跟踪将减少每英寸的损耗。因为我的跟踪仅是~500毫秒长，与硬件指南中提到的“多达3”相反。从一些计算来看，我每英寸的损耗是推荐线的两倍。仅此一点就表明，由于6倍短的跟踪，接受更多的损失是很好的。第二个原因是由于蚀刻因子和A~+/-2MIL容限对12Ω线的阻抗的影响比5MIL迹线小得多。我知道你可以发出阻抗并追踪宽度到PCB工厂，他们会通过额外的工作来控制它。尽管如此，使用更宽的轨迹似乎更聪明。评论？
我的想法是把宽度增加到一个合理的10-12MIs的建议，并生活在我的50欧姆路由层之一损失。我绝对不想路由19MIL跟踪（例如GPIF总线），如DVK GeBER中所示，特别是考虑到它们应该间隔至少3W（~60MILS！）有效隔离。
2）我仍然没有答案存根如何影响性能。附上的是英特尔的展示，展示了一种B型连接器正在与CyPress推荐进行布线。第6页和第13页显示一个通孔连接器在与部件相同的一侧布线。
我非常感谢任何人的输入/经验。
谢谢-史提夫
2-4SISBB-DEVCONNY设计规范
1.3兆字节



     以下为原文
   After spending some time reading on the matter, I'm starting to answer my own questions:
    1) I believe there are two main reasons for why a 12/8/12 90 Ohm differential edge-coupled microstrip was used. These have to do with losses and tolerances. A wider trace will have less loss per inch because of the skin-effect at the ~5GHz USB transmit/receive frequencies. Since my trace is only ~500mils long, as opposed to the up to ~3" mentioned in the hardware guide. From some calculations, I was about twice as lossy per inch than the recommended lines. This alone suggests that it is fine to accept a bit more loss due to the 6x shorter trace. The second reason I believe has to do with simple trace tolerances due to etch factor and the fact that a ~+/- 2mil tolerance will effect the impedance a lot less on a 12 mil trace than a 5mil trace. I know you can call out impedances and trace widths to the pcb fab and they'll go through extra work to control it. Nonetheless, it seems smarter to use a wider trace. Comments?
    My thought is to increase the width to a reasonable 10-12mils as suggested and live with the loss of one of my 50 ohm routing layers. I definitely don't want to route 19mil traces (for the GPIF bus, for example) as shown in the DVK gerbers, especially considering that they should be spaced at least 3w (~60mils!) for effective isolation. 
    2) I still don't have an answer to how the stub will effect performance. Attached is a presentation from intel showing a b-type connector being routing against the Cypress recommendation. Pages 6 and 13 show a through hole connector being routed on the same side as the component.. 
    I would highly appreciate any input / experiences from anyone on this!
    thanks - Steve

•   2-4_SSUSB_DevCon_DesignGuidelines_Heck.pdf 1.3 MB  
  
  

你好，
只要你得到90欧姆微分阻抗，那么你的痕迹宽度是好的。较宽的轨迹将具有较低的衰减，但在您的示例中的路由距离很小，因此任何衰减将是最小的。我已经在两个多氯联苯上使用6密耳宽度的轨迹宽度，它工作得比你的例子稍长。
PCB制造将知道他们自己的过程，所以如果你指定6密耳的痕迹，他们将加宽他们，以弥补任何过度蚀刻。较薄的痕迹唯一的问题是，如果你在顶部和底层使用较重的铜，那么你可以得到痕迹的切割。
对于GPIO/GPIF信号使这50欧姆，但如果你发现它们是两个宽，那么PCB的堆叠将需要看。或者，如果这些痕迹非常短，你可能不需要IMEDENCE匹配它们。经验法则是如果跟踪延迟是上升时间的1/6，那么就不必担心阻抗匹配。
我有两个USB 3 PCB制造。在一个，我使用通孔，使UBB的护符没有高速信号上的任何存根。这是一个简单的路由。在另一个原型板上，FX3和USB B连接器在同一侧，并直接将线路连接到连接器，在高速线路中创建了一个小存根。两个PCB都运行良好，虽然我怀疑一个存根将更糟的EMC的目的。
索达法尔



     以下为原文
  Hi,
    So long as you get the 90 ohm differential impedance then your trace widths are fine. The wider traces will have lower attenuation but the routing distance in your example is small so any attenuation will be minimal. I have routed the trace widths on two pcbs using 6 mil widths and it works well - over slightly longer distances than your example.
    The PCB manufacture will know their own process so if you specifiy 6 mil traces  they will widen them to compensate for any over etching. The only problem with the thinner traces is if you are using heavier  copper on the top and bottom layers then you can get under cutting of the traces.
    For the GPIO/GPIF signals make these 50 ohms but if you find they are two wide then the stackup of the PCB will need looked at. Alternatively if these traces are very short you may not need to imedance match them. Rule of thumb is if the trace delay is 1/6 of the rise time then you don't need to worry about impedance matching
    I  have two USB 3 pcbs made. On one I used vias so that the USB B conector did not have any stubs on the high speed signals. The routing of this was straightforward. On another prototype boardthe FX3 and USB B connector were on the same side and I wired the traces directly to the connector which created a small stub in the high speed lines. Both pcbs worked well although I suspect that the one with the stubs will be worse for EMC purposes.
    Sodafarl

Sodafarl
你给了我惊人的消息，非常感谢！
要知道你已经成功地实施了这些技术，并创建了一个工作板是非常出色的，没有什么比我的书中的经验更好的了：
我非常感激，
史蒂夫



     以下为原文
   [size=10.909090995788574px]Sodafarl,
    You've given me amazing news, thank you very much!
    To know that you have successfully implemented these techniques and created a working board is excellent, nothing beats experience in my books :)
    I appreciate this very much,
    Steve