斯巴达3A锁定崩溃

实际上，这确实听起来像JTAG状态机问题。
JTAG时钟（TCK）如何？
终止？
如果它被拉起，我会建议把它拉到地面以防止
电源故障时钟边缘的可能性。
问候，
的Gabor
-  Gabor
在原帖中查看解决方案



以下为原文

So this does in fact sound like a JTAG state machine issue.  How is the JTAG clock (TCK)
terminated?  If it is pulled up, I would suggest instead pulling it to ground to prevent the
possibility of clock edges on a power glitch.
 
Regards,
Gabor
-- GaborView solution in original post

嗨，
我忘了提到FPGA设置为主串行模式。
Prom是Xilinx XCF01S。
它们是链中唯一的设备。



以下为原文

Hi,
 
I forgot to mention that the FPGA is set to master serial mode. The Prom is a Xilinx XCF01S. They are the only devices in the chain.

看门狗真的有效吗？
如果RF瞬态足以扼杀FPGA，那么它很可能也会打击看门狗。
----------------------------是的，我这样做是为了谋生。



以下为原文

Is the watchdog actually working? If the RF transient is sufficient to kill the FPGA then it's likely it's also whacking the watchdog.----------------------------Yes, I do this for a living.

我可以使用PROG_B线上的手动按钮来尝试重置FPGA。
按下它不起作用。
我已经测量了信号进入FPGA并检查按下按钮时信号是否变低。



以下为原文

There is a manual button on the PROG_B line I can use to try to reset the FPGA. Pressing it does not work.
 
I have measured the signal into the FPGA and checked that the signal is going low when the button is pressed.

由于PROG_B重置了FPGA上的所有内容，我猜你
这里有严重的闩锁状况。
你能监控电源吗？
当发生这种情况时，看看它们是否超出了最大值
设备的评级？
你确认所有的电源轨都回来了
事件发生后的正常水平？
是否连接了FPGA的某些引脚 
直接连接到可能作为天线接收RF的长导线？
如果是这样
这些信号是否可以用像双极性这样不太敏感的部分进行缓冲
结晶体管？
对不起，问题多于答案，
的Gabor
-  Gabor



以下为原文

Since PROG_B resets pretty much everything on the FPGA, I am guessing you
have a serious latch-up condition here.  Can you monitor the power supply
rails when this happens to see if they are going well beyond the maximum
ratings of the device?  Have you confirmed that all power rails go back to
normal levels after the event?  Are there some pins of the FPGA connected
directly to long wires that may act as antennas to pick up the RF?  If so
could these signals be buffered with a less sensitive part like bipolar
junction transistors?
 
Sorry more questions than answers,
 
Gabor
-- Gabor

还有一个问题需要确定它是FPGA还是Flash芯片
造成这个问题。
当你闩锁并且脉冲PROG_B为低时，
FPGA是否在CCLK引脚上输出时钟？
如果不是问题必须
在FPGA中。
如果是这样，重置闪光灯可能会出现问题。
难道
你可以根据INIT的配置指南将它们连接起来
FPGA的引脚与闪存的复位输入相连？
-  Gabor



以下为原文

One more question to determine whether it is the FPGA or the Flash chip
causing the problem.  When you get the latch up and pulse PROG_B low,
does the FPGA output a clock on the CCLK pin?  If not the problem must
be in the FPGA.  If so there could be an issue resetting the flash.  Did
you hook them up according to the configuration guide with the INIT
pin of the FPGA tied to the reset input of the flash?
-- Gabor

由于FPGA在它们附近的盒子里，我无法在事件期间监视电源。
如果我确实试图监控它们，我最终会连接很长的电线，这会吸收很多噪音。
我附近有一个望远镜，即使探头短路，我也看到很多噪音。
FPGA锁定后，电源会测量正确的电压。
（3.3V和1.2V）。
每个1.2V电源引脚在PCB正下方的PCB底部的电源平面上通过100nF和10nF去耦。
每个3.3V引脚通过一个10nF电容去耦，每侧有100nF电容。
有一些很长的迹线进入FPGA，但这些迹线位于电源和接地层之间PCB的内部信号层上。
当电路板布局时，它们被放置在平面之间以帮助屏蔽这些迹线。
由于系统的布局，我无法进入FPGA内存芯片，因为还有另一个板（PSU）。
Prom接口的布局如配置用户指南UG332中的图3-2所示。



以下为原文

I can not monitor the supplies during the events as the FPGA is in a box near them. If I did try to monitor them I would end up with long wires attached which would pick up a lot of noise. I have had a scope near by and I see a lot of noise even with the probe shorted. After the FPGA has locked up the power supplies measure the correct voltages. (3.3V and 1.2V). Each 1.2V power pin is decoupled by a 100nF and a 10nF on a power plane on the underside of the PCB directly below the FPGA. Each 3.3V pin is decoupled by a 10nF capacitor with 100nF capacitors on each side.
 
There are a few long traces going to the FPGA but these are on inner signal layers of the PCB between the power and ground planes. When the board was laid out these were put between the planes to help screen these traces.
 
Due to the layout of the system I can't get at the FPGA - memory chip as there is another board (the PSU) in the way. The layout of the Prom interface is as specified in figure 3-2 in UG332 the configuration user guide.
 

我修改了一个单元，允许我在崩溃后连接电源进行调试。
从FPGA到PROM没有任何通信迹象 - 所有线路都保持在3.3V。
连接到JTAG端口并使JTAG链初始化恢复了正常功能。
FPGA是否有可能在JTAG序列中“卡住”？



以下为原文

I have modified a unit to allow me to connect a power source to debug after it has crashed.
 
There is no sign of any communications from the FPGA to the PROM - all lines remained at 3.3V. Connecting to the JTAG port and initalising the JTAG chain restored normal functionality. Would it be possible for the FPGA to get "stuck" in the JTAG sequance?

当你说所有线路保持在3.3V时，是否包括DONE信号？
我第一次想到卡住是因为在某种情况下它可能是可能的
误读模式引脚。
我记得这些只是在FPGA时才采样
退出上电复位。
如果模式引脚没有直接连接到地或a
FPGA使用的电源来检测上电复位，它们可能被错误读取而导致
FPGA进入Master Serial以外的模式。
无论感测到何种模式
在上电时，FPGA总是可以通过JTAG进行编程。
它仍然令人费解
PROG_B断言不会解决问题，除非存在其他一些问题
系统中的状态 - 也许PROM本身“卡住了”。
你有没有尝试重新编程？
通过JTAG编程后，PROM中的FPGA？
-  Gabor



以下为原文

When you say all lines remain at 3.3V, does that include the DONE signal?
 
My first thought about getting stuck is that it might be possible under some condition
to mis-read the mode pins.  As I recall these are only sampled at the time the FPGA
exits power-on reset.  If the mode pins are not tied directly to either ground or a
supply used by the FPGA to sense power-on reset they could be mis-read, causing
the FPGA to enter a mode other than Master Serial.  Regardless of the mode sensed
on power-up, the FPGA can always be programmed via JTAG.  It's still puzzling why
PROG_B assertion would not fix the problem unless there is some other stored
state in the system - perhaps the PROM itself is "stuck."  Did you try to re-program
the FPGA from the PROM after you programmed it via JTAG?
-- Gabor

我没有直接测量DONE信号，但由于我在该线路上有一个未点亮的LED，我可以说DONE信号一直很低。
模式引脚分别通过靠近引脚的过孔分别连接到接地层。
当我通过JTAG端口连接时，我没有编程FPGA或PROM。
我在边界扫描模式下使用iMPACT，右键单击背景并从选项中选择“初始化链”。
这导致它在询问每个设备应编程的文件之前轮询JTAG链并从每个设备获取ID。
在对链条进行轮询后，从PROM加载的FPGA开始工作 -  iMPACT仍然在屏幕上提示应该编程的内容。
在过去，我不得不完全重启系统。
在每种情况下，FPGA都已从PROM正确编程。



以下为原文

I did not directly measure the DONE signal, but as I have a LED on that line that was not lit I can say that the DONE signal must have been low.
 
The mode pins are each tied to the ground plane separatly through vias close to the pins.
 
When I connected via the JTAG port I did not program either the FPGA or the PROM. I used iMPACT in boundary scan mode, right clicked on the background and chose "Initalize Chain" from the options. This causes it to poll the JTAG chain and get the ID from each device before asking what file should be programmed into each. After it had polled the chain the FPGA loaded from the PROM and started working - iMPACT still had the prompt on the screen asking what should be programmed.
 
In the past I have had to completly power cycle the system. The FPGA has programmed from the PROM correctly in each case.

实际上，这确实听起来像JTAG状态机问题。
JTAG时钟（TCK）如何？
终止？
如果它被拉起，我会建议把它拉到地面以防止
电源故障时钟边缘的可能性。
问候，
的Gabor
-  Gabor



以下为原文

So this does in fact sound like a JTAG state machine issue.  How is the JTAG clock (TCK)
terminated?  If it is pulled up, I would suggest instead pulling it to ground to prevent the
possibility of clock edges on a power glitch.
 
Regards,
Gabor
-- Gabor

目前，它们使用FPGA中的内部电阻选项进行上拉。
当问题出现时，我试过外部拉起没有效果。
我没有试过把它们拉低。
我可以试着把它拉下来看看会发生什么。



以下为原文

Currently they are pulled up using the internal resistors option in the FPGA. When the problem manifested I tried external pull ups with no effect. I have not tried pulling them low. I can try pulling it down and see what happens.

我修改了一个似乎经常崩溃的单元来移除上拉并在编程文件选项中配置内部下拉。
结果是它不再锁定，虽然偶尔会重新加载程序（导致故障），这解决了锁存问题。
非常感谢。
尼尔



以下为原文

I modified a unit that seemed to crash reasonably often to remove the pull ups and configured the internal pull downs in the programming file options.
 
The result is that it no longer latches up, although it does reload the programme occasionally (causing a glitch) this has solved the latch up issue.
 
Many thanks.
 
Neil