帮助Spartan 3AN中的全局时钟和复位

嗨，即使我是所有FPGA和VHDL的新手，我只能回答你的一些问题。
你问如何将你的重置端口连接到全局重置......我建议把这个端口连接到主板上的任何其他按钮，这样当你按下这个按钮时，会发出一个高信号，
所有信号都设置为初始值，对于全局复位，我认为它仅用于复位电路板，使其处于可以将位文件加载到Flash的状态。
这只是我的理解而已。
全局时钟，只需要提前计划，并为E12分配时钟端口，就像使用内部时钟一样 - 我假设您正在使用ISE，当您点击新源时我希望您已经注意到ISE允许您使用的各种文件
添加一个选项将是IP核生成器向导单击它，在进一步的步骤中将看到您可以实际要求Xilinx创建并为您提供的各种组件。
在那一个选项将是与FPGA相关的组件点击它，你可以看到时钟组件点击你将获得DCM（数字CLOCK管理器）选项，如果你使用这个DCM你可以创建组件，你可以指定批量属性
，如果你说外部源（这个组件的UCF将被创建，E12将自动生成），一个这样的属性将是从你指定的源分配一个时钟，你可以提到的其他属性就是你
现在想用外部时钟源信号做，你可以乘以2倍并使其加倍，你可以将它分成几个值，你可以相移它等等...........最后
当您完成分配此DCM时（您还将为其命名，该名称将成为此组件的名称）.....现在您可以将此时钟用作设计中的组件，就像在VHDL中使用Structural Progamming一样。
直到上周我才知道所有这些......但是现在我知道的很少.....所以它不是那么难以学习所有它需要的只是时间.......我推荐
您了解了可供您的Spartan学习时钟的各种DCM ................
并且模拟和综合根本不会相互接触，所以即使你在模拟中得到结果也不能保证你的最终模块能够工作......我现在已经遇到了类似的问题.......尝试
要解决这个问题....
我在艰难之路中学到的一件事是你必须正确理解CLock并重置信号......并理解并修复它们在你的设计中扮演的角色..........
提示：
尝试将行为和结构设计理解为起点.......如果你得到行为，那么结构只是将这些行为事物联系在一起..............和alawys开始
用纸，铅笔和橡皮擦.......将整个任务分成一个页面上的较小模块，然后在另一个页面上尝试将所有这些功能分开的思想连接在一起......接下来当你确信你的
连接很好.....开始给每个小单位一个行为........
我可以理解心态新手通常会这就是为什么我的描述就像一个外行的谈话......我希望这里的一些大师会给你更坚实的答案......比我的...... :)



以下为原文

Hi, even I'm new with all the FPGA and VHDL stuff, I can answer to only some of your questions.
 
You ask how to connect your reset port to Global reset...... what I suggest is connect this port to any other Button on the board, so on using that button, when you press this button a high signal is sent,  with which all your signals areset to the initial values, as for the Global reset, I think that it is used only to reset the board bring it to a  state from where you can load the bit file into the Flash. This is just my understanding only.
 
Global clock, just go to Plan ahead and assign the clock port with E12 as for using internal clocks - I assume that you are using ISE and when you click on New Source I hope you have noteiced the various kinds of files which the ISE allows you to add in that one option will be IP Core generator Wizard click on it and in further steps will see the various kinds of components you can actually ask Xilinx to create and give for you. In that one option is going to be FPGA related components click on it and you can see clocking componenets click on that you will get DCM(Digital CLock Managers) option if you use this DCM you can create components for which you can specify a lot properties, and one such property will be to assign a clock, from a source you specify, if you say external source (An UCF for this component will be created and E12 will be automatically), and the other properties that you can mention is what you whould like to do with the external clock source signal now, you can multiply with 2 times and make it double, you can divide it bsome values, you can phase shift it and so on........... finally when you finsh assigning this DCM(You will also give it a name which becomes the name of this component)..... now you can use this clock as a component in your design like the way you do in Structural Progamming in VHDL.
 
Till last week I was'nt knowing all of  this....... but now I know  little..... so its not that tough to learn all it needs is just time....... I reccommend  you read about the various DCMs available for your Spartan to learn about clocks................ 
 
And simulation and Synthesis dont touch each other at all so even if you get results in simulation there is no guarantee that your final module works or not.... I'm struck with a similar problem now....... trying to fix it....
 
One thing I have learnt in a hardway is that you have to understand the CLock and reset signals PROPERLY...... and understand and fix what role they play in your design..........
 
Tips: 
 
Try to understand the Behavioaral and structural designing as a starting point....... if you get behavioral then Structural is just attachingand linking these behavioural things together..............and alawys start with a paper, pencil and eraser....... divide the entire task into smaller modules on one page, next on another page just try connnecting all these functionally split thinkgs together..... next when you are convinced that your connections are good..... start giving a behaviour to each small unit........
 
I can understand the state of mind Newbies will usually be thats why my description is like a layman's talk...... I hope some Gurus here will give you more solid answers... than mine..... :)
 
 
 

这些可以是很好的资源：
http://forums.xilinx.com/xlnx/blog/article?message.uid=12856（危险的异步重置！）http://www.xilinx.com/support/documentation/white_papers/wp272.pdf（Get Smart
关于重置思考本地，非全局）重置也在XST用户指南（例如xst.pdf）和许多设备系列的用户指南（搜索“GSR”）中讨论。
BT



以下为原文