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我刚刚掌握了FPGA和VHDL，请原谅我们提出的基本问题。 基本上，我发现重置的整个问题有点令人困惑。 据我了解，当FPGA首次上电时，它会下载其配置，同时保持全局复位线为高电平。 这是一个专门用于任务的特殊网络 - 全局设置/重置。 配置完成后，该线路被置低，以允许FPGA开始其新编程的功能。 假设这是正确的，那么我理解。 在我的VHDL中，如果我有一个简单的顶级模型，其中一个进程对时钟和复位信号很敏感，我可以像这样写它...... 信号时钟：std_logic; 信号重置：std_logic; some_logic：进程（时钟，重置） 开始 if（reset ='1'）然后 - 将信号设置为所需的初始值 elsif rising_edge（时钟）然后 - 做正常的操作 万一; 结束过程some_logic; 通过UCF文件（或PlanAhead），我将时钟信号设置为主振荡器输入引脚。 在Spartan 3AN板的情况下，其引脚E12。 我是否应该特别告诉合法人员使用全局时钟资源？它似乎认识到它会自动查看设计报告，但这仍然适用于更复杂的设计吗？ 我怎么告诉我在VHDL中使用clockresouses？ 以上工作正常，没有复位信号。 但随着它包括在内，我有什么吸引力？ 或者，如何将我的复位信号连接到全局置位/复位？这实际上是我想做的吗？我不需要外部复位信号，所以不需要将它连接到任何特定的引脚。 我只需要在配置完成后将信号置于其初始状态（或者实际上，在配置期间）。 我的另一个困惑是这一切如何与模拟联系在一起。 修复上述问题后，全局设置/重置信号是否仍然存在于模拟中，或者您是否需要在测试平台中专门实例化？ 对不起所有的问题，但我发现文档要么令人困惑，要么只是缺乏使用VHDL如何使用时钟和重置的简单描述。 非常感谢任何建议或意见， 问候 罗布史密斯 以上来自于谷歌翻译 以下为原文 Hi there, I'm just getting to grips with FPGA's and VHDL, so please forgive the very basic questions. Basically, I'm finding the whole issue of resets to be somewhat confusing. As I understand it, when the FPGA first powers on, it downloads its configuration, whilst holding a global reset line high. This is a special net specifically for the task - the global set/reset. When configuration finishes, this line is de-asserted to allow the FPGA to begin its newly programmed function. Assuming that is correct, then I understand that. In my VHDL, if I have a simple top-level model with a single process that is sensitive to a clock and reset signal, I can write it like this... signal clock: std_logic; signal reset: std_logic; some_logic: process (clock, reset ) begin if ( reset = '1' ) then -- set signals to required initial value elsif rising_edge(clock) then -- do normal operation end if; end process some_logic; Via the UCF file (or PlanAhead), I've set the clock signal to connect to the master oscillator input pin. In the case of the Spartan 3AN board, its pin E12. Should I be specifically telling the synthesiser to use the global clock resources for this? It seems to recognise it automatically looking at the design report, but does that still work for more complex designs? And how would I tell it to use the clock resouses in VHDL? The above works fine without the reset signal. But with it included, what do I attach it to? Or rather, how do I attach my reset signal to the global set/reset? And is that actually what I want to do? I don't require an external reset signal, so don't need to attach it to any particular pin. I just need to put my signals into their initial state after configuration completes (Or really, for the duration of configuration). My other confusion is how this all ties into simulation. Once the above problem is fixed, will the global set/reset signal still exist in simulation, or do you need to instatiate it specifically in your testbench? Sorry for all the questions, but I've been finding the documentation either confusing or just lacking in simple descriptions of how to use the clocks and resets using VHDL. Thanks very much for any advice or suggestions, Regards Rob Smith 
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嗨，即使我是所有FPGA和VHDL的新手，我只能回答你的一些问题。
你问如何将你的重置端口连接到全局重置......我建议把这个端口连接到主板上的任何其他按钮，这样当你按下这个按钮时，会发出一个高信号， 所有信号都设置为初始值，对于全局复位，我认为它仅用于复位电路板，使其处于可以将位文件加载到Flash的状态。 这只是我的理解而已。 全局时钟，只需要提前计划，并为E12分配时钟端口，就像使用内部时钟一样 - 我假设您正在使用ISE，当您点击新源时我希望您已经注意到ISE允许您使用的各种文件 添加一个选项将是IP核生成器向导单击它，在进一步的步骤中将看到您可以实际要求Xilinx创建并为您提供的各种组件。 在那一个选项将是与FPGA相关的组件点击它，你可以看到时钟组件点击你将获得DCM（数字CLOCK管理器）选项，如果你使用这个DCM你可以创建组件，你可以指定批量属性 ，如果你说外部源（这个组件的UCF将被创建，E12将自动生成），一个这样的属性将是从你指定的源分配一个时钟，你可以提到的其他属性就是你 现在想用外部时钟源信号做，你可以乘以2倍并使其加倍，你可以将它分成几个值，你可以相移它等等...........最后 当您完成分配此DCM时（您还将为其命名，该名称将成为此组件的名称）.....现在您可以将此时钟用作设计中的组件，就像在VHDL中使用Structural Progamming一样。 直到上周我才知道所有这些......但是现在我知道的很少.....所以它不是那么难以学习所有它需要的只是时间.......我推荐 您了解了可供您的Spartan学习时钟的各种DCM ................ 并且模拟和综合根本不会相互接触，所以即使你在模拟中得到结果也不能保证你的最终模块能够工作......我现在已经遇到了类似的问题.......尝试 要解决这个问题.... 我在艰难之路中学到的一件事是你必须正确理解CLock并重置信号......并理解并修复它们在你的设计中扮演的角色.......... 提示： 尝试将行为和结构设计理解为起点.......如果你得到行为，那么结构只是将这些行为事物联系在一起..............和alawys开始 用纸，铅笔和橡皮擦.......将整个任务分成一个页面上的较小模块，然后在另一个页面上尝试将所有这些功能分开的思想连接在一起......接下来当你确信你的 连接很好.....开始给每个小单位一个行为........ 我可以理解心态新手通常会这就是为什么我的描述就像一个外行的谈话......我希望这里的一些大师会给你更坚实的答案......比我的...... :) 以上来自于谷歌翻译 以下为原文 Hi, even I'm new with all the FPGA and VHDL stuff, I can answer to only some of your questions. You ask how to connect your reset port to Global reset...... what I suggest is connect this port to any other Button on the board, so on using that button, when you press this button a high signal is sent, with which all your signals areset to the initial values, as for the Global reset, I think that it is used only to reset the board bring it to a state from where you can load the bit file into the Flash. This is just my understanding only. Global clock, just go to Plan ahead and assign the clock port with E12 as for using internal clocks - I assume that you are using ISE and when you click on New Source I hope you have noteiced the various kinds of files which the ISE allows you to add in that one option will be IP Core generator Wizard click on it and in further steps will see the various kinds of components you can actually ask Xilinx to create and give for you. In that one option is going to be FPGA related components click on it and you can see clocking componenets click on that you will get DCM(Digital CLock Managers) option if you use this DCM you can create components for which you can specify a lot properties, and one such property will be to assign a clock, from a source you specify, if you say external source (An UCF for this component will be created and E12 will be automatically), and the other properties that you can mention is what you whould like to do with the external clock source signal now, you can multiply with 2 times and make it double, you can divide it bsome values, you can phase shift it and so on........... finally when you finsh assigning this DCM(You will also give it a name which becomes the name of this component)..... now you can use this clock as a component in your design like the way you do in Structural Progamming in VHDL. Till last week I was'nt knowing all of this....... but now I know little..... so its not that tough to learn all it needs is just time....... I reccommend you read about the various DCMs available for your Spartan to learn about clocks................ And simulation and Synthesis dont touch each other at all so even if you get results in simulation there is no guarantee that your final module works or not.... I'm struck with a similar problem now....... trying to fix it.... One thing I have learnt in a hardway is that you have to understand the CLock and reset signals PROPERLY...... and understand and fix what role they play in your design.......... Tips: Try to understand the Behavioaral and structural designing as a starting point....... if you get behavioral then Structural is just attachingand linking these behavioural things together..............and alawys start with a paper, pencil and eraser....... divide the entire task into smaller modules on one page, next on another page just try connnecting all these functionally split thinkgs together..... next when you are convinced that your connections are good..... start giving a behaviour to each small unit........ I can understand the state of mind Newbies will usually be thats why my description is like a layman's talk...... I hope some Gurus here will give you more solid answers... than mine..... :) |
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这些可以是很好的资源：
http://forums.xilinx.com/xlnx/blog/article?message.uid=12856（危险的异步重置！）http://www.xilinx.com/support/documentation/white_papers/wp272.pdf（Get Smart 关于重置思考本地，非全局）重置也在XST用户指南（例如xst.pdf）和许多设备系列的用户指南（搜索“GSR”）中讨论。 BT 以上来自于谷歌翻译 以下为原文 These can be good resources: http://forums.xilinx.com/xlnx/blog/article?message.uid=12856 (That Dangerous Asynchronous Reset!) http://www.xilinx.com/support/documentation/white_papers/wp272.pdf (Get Smart About Reset Think Local, Not Global) Reset is also discussed in the XST User Guide (e.g. xst.pdf) and in many device families' user guide (search for "GSR"). bt
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