Spartan 3AN入门套件

我快速查看了你的代码，我猜你还没有模拟它。
该
我首先看到的是，一旦FPGA出现，您就会开始写入ADC
配置。
如果ADC未处于准备状态，则可能会出现问题
收到命令。
例如，芯片选择和SPI时钟线是什么
在FPGA配置时做什么？
我面前没有你的电路板原理图。
所以我不确定它有什么ADC
它。
您能否发布部件号，如果不是太多要问，请链接到
数据表。
数据和数据之间的对齐也可能存在问题
时钟，但这取决于ADC用于捕获数据的时钟边沿。
许多SPI设备可以使用任一边缘并尝试检测基于哪个边缘使用
芯片选择和SPI时钟之间的时序关系。
确保你是
满足SPI时钟的建立和保持要求。
从我看到的，你的
数据在SPI时钟的上升沿同时切换。
无论如何，模拟设计。
尽管很简单，但你仍然可以学到一些东西
看模拟波形。
就像SPI_MOSI在启动时所做的那样？
-  Gabor



以下为原文

I took a quick look at your code, and I'm going to guess you haven't simulated it.  The
first thing I see is that your write to the ADC starts as soon as the FPGA comes out
of configuration.  This could be problematic if the ADC was not in a state ready to
receive the command.  For example what are the chip select and SPI clock lines
doing while the FPGA is configuring?
 
I don't have your board schematic in front of me.  So I'm not sure what ADC it has on
it.  Could you please post the part number and if it's not too much to ask, a link to
the data sheet.  There may also be problems with the alignment between data and
clock, but that depends on which edge of the clock your ADC uses to capture data.
Many SPI devices can use either edge and try to detect which edge to use based on
the timing relationship between chip select and the SPI clock.  Make sure you are
meeting setup and hold requirements to the SPI clock.  From what I see, your
data is switching at the same time as the rising edge of the SPI clock.
 
In any case, simulate the design.  As simple as it is, you can still learn something
looking at the simulation waveform.  Like what is SPI_MOSI doing at start-up?
-- Gabor

当然。
该入门工具包具有凌力尔特技术的2通道模拟捕获电路。前置放大器的数据表是：http：//cds.linear.com/docs/en/datasheet/6912fa.pdf，ADC的一个是：http：/
/cds.linear.com/docs/en/datasheet/14071fb.pdf
我已经模拟了代码并得到了与用户手册中提供的波形非常相似的波形。您可以查看手册，第71-77页。这是链接：http：//www.xilinx.com/support
/documentation/boards_and_kits/ug334.pdf
非常感谢再次。:)



以下为原文

Sure. The starter kit has this 2 Channel Analog Capture Circuit from Linear technology.
The datasheet for the preamplifier is: http://cds.linear.com/docs/en/datasheet/6912fa.pdf 
and the one for the ADC is: http://cds.linear.com/docs/en/datasheet/14071fb.pdf
And I have simulated the code and got the waveforms quite similar to the ones provided in the user manual. 
U can take a look at the manual, pages 71 - 77. Here's the link: http://www.xilinx.com/support/documentation/boards_and_kits/ug334.pdf
Thanks a lot once again.
:)

我的模拟看起来不像用户手册中的波形。
见附图。
对于
一方面，手册中的时序图以芯片选择高电平开始，其第一个下降沿为30 ns
在SPI_SCK的第一个上升沿之前。
你的代码开始时芯片选择已经很低，所以你有
不知道在配置过程中它是如何转换的。
接下来我看到MOSI是第三个直到第二个
SPI_SCK的上升沿，我再也没有看到用户指南中显示的30 ns设置时间。
对于任何状态逻辑在空闲状态下出现通常是个好主意，即芯片选择被置低
（高）和SPI_SCK低。
此外，无论您是否在FPGA上有一个实际的复位引脚，这都是很好的做法
具有任何状态逻辑的复位输入。
您可以使用简单的班次生成自己的内部重置
寄存器初始化为全1并在配置后移位为零。
或者您可以将所有较低级别绑定
模块在顶层重置为'0'，但至少可以使用重置进行模块级仿真。
另外，查看LTC1407-1数据手册中的时序图，CONV脉冲大致相同
宽度为SPI_SCLK，而您的宽度与系统时钟的宽度相同。
我正在猜测
这个“欠幅”的CONV脉冲被ADC过滤掉了。
-  Gabor



以下为原文

My simulation did not appear to look like the waveforms in the user's manual.  See attached image.  For
one thing the timing diagram in the manual starts with chip select high with its first falling edge 30 ns
before the first rising edge of SPI_SCK.  Your code starts with chip select already low, so you have
no idea how it transitioned there during configuration.  Next I see that MOSI is tristate until the second
rising edge of SPI_SCK, and again I don't see the 30 ns setup time as shown in the user guide.
 
It's generally a good idea for any state logic to come up in an idle condition, i.e. chip select de-asserted
(high) and SPI_SCK low.  Also whether or not you have an actual reset pin on the FPGA, it's good practice
to have a reset input to any state logic.  You can generate your own internal reset using a simple shift
register that initializes to all 1's and shifts in zero after configuration.  Or you can just tie all the lower level
module resets to '0' at the top level, but at least you can use the reset for module-level simulation.
 
Also looking at the timing diagrams in the LTC1407-1 data sheet, the CONV pulse is about the same
width as the SPI_SCLK, while yours appears to have the same width as your system clock.  I'm guessing
that this "runt" CONV pulse is getting filtered out by the ADC.
-- Gabor

感谢Gabor指出我的代码中的错误。
我刚刚开始使用VHDL和FPGA，事实上，在某些情况下，我无法提供手册中给出的确切时序。
我会修改代码并很快回复你。
非常感谢，再一次。



以下为原文

Thanks Gabor for pointing out the errors in my code. I have just started working with VHDL and FPGAs, and indeed I have not been able to provide the exact timings, as given in the manual, in some cases. I will modify the code and get back to u very soon. Thanks a lot, once again.

感谢Gabor的所有帮助。
我和Sayak一起做这个项目。
我修改了代码以完全复制数据表中给出的内容。
虽然时钟频率不同，但根据我们的需要，但在此代码中已经满足了对信号施加的最小限制。
我已经附加了模拟测试平台以及架构代码以及此消息。
它无法正常工作，我从ADC获得零输出。 
通过使用精密探头和万用表确定放大器输出的问题，可以直接从我们的Spartan 3AN入门套件上的放大器的输出引脚测量放大器的电压输出。
观察结果如下.. 
1）我在为此目的分配的套件的输入端口给出了2.08伏的直流电压。 
2）如果你看一下数据表，它会显示输入值与1.65伏的参考值进行比较，并相应地设置直流偏移。 
3）所以，如果我给出2.08伏输入。
放大器级将获得（2.08-1.65）伏或0.43伏的输入。 
4）我在模拟中的代码，如果你观察，将增益设置为（-1）。 
5）事实：放大器级输出端测得的电压约为1.7伏。 
6）如果增益为-4是不可能的话，这可能存在。并且放大器没有-4增益的任何规定。如果你看到数据表增益只能取0，-1的值， -
2，-5，-10，-20，-50，-100。 
期待您的回复Gabor和任何可以帮助我们解决这个问题的人。
谢谢。
- 萨米克
adc_communication_test.vhd 8 KB
tb.vhd 4 KB



以下为原文

 
       Thank you for all the help Gabor. I am doing this project along with Sayak. I have modified the codes to exactly replicate what is given there in the datasheet. Although clock frequencies are different, as per our need, but the minimum restrictions imposed on the signals have been fulfilled in this code. I have attached the simulation testbench and also the architecture code along with this message. It is not working properly and I am getting a zero output from the ADC.
       A problem was located with the amplifier output by using a fine probe and a multimeter the voltage output from the amplifier could be measured directly from the output pins of the amplifier on our Spartan 3AN Starter Kit. The observations are as follows..
     1) I gave a DC voltage of 2.08 volts at the input port of the kit assigned for the purpose.
     2) If you have a look at the datasheet it shows that a comparison is done of the input value with 1.65 volts of reference value and a DC offset is set accordingly .
     3) So if I give a 2.08 volt input. The amplifier stage is going to get an input of (2.08-1.65) volts or 0.43 volts.
     4) my code in the simulation, if you observe, sets the gain to (-1) .
     5) FACT: the voltage measured at the output of amplifier stage was around 1.7 volts.
     6) this could exist if the gain is -4 which is impossible.. And the amplifier doesn't have any provision for -4 gain.If            you see the data-sheet gains can only take the values of 0, -1, -2, -5, -10, -20, -50, -100.
 
     Looking forward to a reply from you Gabor and anybody who can help us out with this problem.
Thank You.
 
-- Samik
            adc_communication_test.vhd ‏8 KB                tb.vhd ‏4 KB

1）我在为此目的分配的套件的输入端口给出了2.08伏的直流电压。
你的意思是指相对于地板的2.08伏？
2）如果你看一下数据表，它会显示输入值与1.65伏的参考值进行比较，并相应地设置直流偏移。
是的，这个1.65V是放大器和ADC的参考。
所以实际上，你的输入是+ 430mV
关于进入放大器的参考，如果你真的将增益设置为-1，那么它应该是
相对于参考电压为-430mV或相对于电路板接地为+ 1.22V。
3）所以，如果我给出2.08伏输入。
放大器级将获得（2.08-1.65）伏或0.43伏的输入。
到目前为止正确。
4）我在模拟中的代码，如果你观察，将增益设置为（-1）。
嗯......还有待证明。
5）事实：放大器级输出端测得的电压约为1.7伏。
这可疑接近1.65伏，除非你的意思是相对于参考电压为1.7V，
哪个会超出范围。
如果你的意思是在地面以上1.7V，那么这是基本的
在电压参考点，并建议放大器处于掉电模式或
“零增益”模式，输入未连接到放大器。
6）如果增益为-4是不可能的话，这可能存在。并且放大器没有-4增益的任何规定。如果你看到数据表增益只能取0，-1的值， -
2，-5，-10，-20，-50，-100。
同样，您需要参考1.65V的放大器，而不是电路板接地。
相对于1.7V
板地表明增益大约为零，而不是-4。
如果增益设置为-4，我会期望放大器输出
处于地面（饱和低），因为它试图乘以0.43 * -4并增加1.65，这将导致
在-.07V，但放大器没有负电源，所以它不能驱动那么低。
-  Gabor



以下为原文

1) I gave a DC voltage of 2.08 volts at the input port of the kit assigned for the purpose.
 
You mean 2.08 volts with respect to board ground I presume?
 
2) If you have a look at the datasheet it shows that a comparison is done of the input value with 1.65 volts of reference value and a DC offset is set accordingly .
 
Yes, this 1.65V is the reference for both the amplifier and the ADC.  So in effect, your input was +430mV
with respect to the reference going into the amplifier, and if you really set the gain to -1 it sould have been
-430mV with respect to the reference or about +1.22V with respect to board ground.
 
3) So if I give a 2.08 volt input. The amplifier stage is going to get an input of (2.08-1.65) volts or 0.43 volts.
 
Correct so far.

 
4) my code in the simulation, if you observe, sets the gain to (-1) .
 
 
Ummm... that is yet to be proven.
 
5) FACT: the voltage measured at the output of amplifier stage was around 1.7 volts.
 
This is suspiciously close to 1.65 volts, unless you mean 1.7V with respect to the reference,

which would put it out of range.  If you mean 1.7V above board ground, then this is essencially

at the voltage reference point, and suggests that the amplifier is in power-down mode or

"zero gain" mode where the inputs are not connected to the amplifier.

 
6) this could exist if the gain is -4 which is impossible.. And the amplifier doesn't have any provision for -4 gain.If you see the data-sheet gains can only take the values of 0, -1, -2, -5, -10, -20, -50, -100.
 
Again, you need to look at the amplifier with reference to 1.65V, not to board ground.  1.7V with respect to

board ground suggests a gain of about zero, not -4.  If the gain were set to -4 I'd expect the amplifier output

to be at ground (saturated low) because it was trying to multiply 0.43 * -4 and add 1.65 which would result

in -.07V, however the amplifier doesn't have a negative power supply so it can't drive that low.

 
-- Gabor

我启动了模拟，（下次你可能发布一个屏幕截图，所以我不需要这样做）
而且您似乎将放大器增益设置为-1并满足放大器的时序。
您可能需要首先检查您的UCF文件是否正确找到与之关联的所有引脚
放大器。
注意，如果SHDN引脚为高电平，或者实际上没有写入放大器增益
由于其他一些引脚排列问题，那么放大器将处于关断模式并且表现良好
非常像你所看到的。
-  Gabor



以下为原文

I fired up the simulation, (next time you could possibly post a screen shot so I don't need to do this)
and it seems that you are setting the amplifier gain to -1 and meeting the timing of the amplifier.
 
You may want to start by checking if your UCF file properly locates all pins associated with the
amplifier.  Note that if the SHDN pin is high, or if you don't actually write the amplifier gain
because of some other pinout issue, then the amplifier will be in shutdown mode and behave
pretty much like you are seeing.
-- Gabor

所有电压均在地电位下测量。
是的，我能理解这一点。
输出为1.7伏，它实际上表明我基本上在输出端获得参考电压，而放大器没有放大或放大器增益为零。
谢谢，我意识到自己的错误。 
但主要问题仍然存在。
增益设置为零，因此这必须是我没有从ADC模块获得任何ADC输出到我的fpga的原因。
所以问题很明显。 
你能看一下模拟吗？
你能发现波形中有任何可能的错误吗？
特别是我为放大器设置增益的部分？
我无法理解这件事我们哪里出错了。 
感谢Gabor的所有努力。
我们非常感谢您的帮助。 
每次我对模拟输入进行采样时，是否必须设置增益？
即。
在每个采样时间间隔？
--Samik



以下为原文

                    All voltages are measured wrt the ground potential. Yes, i can understand this. The output being 1.7 volts it actually shows that i am basically getting my reference voltage at the output and the amplifier is not amplifying or an amplifier gain of zero has been set. Thank you, i have realized my mistake.
 
                    But the main problem still remains. The gain setting is zero and so this must be the reason why i am not getting any ADC output into my fpga from the ADC module. So the problem is clear.
 
                     Can you please have a look at the simulation?  Can you find out any possible error in the waveform? Especially the part where i have set the gain for the amplifier? I can't understand where we are going wrong with this thing.
                     Thank you for all the effort Gabor. We really appreciate your help.
 
                      Do i have to set the gain everytime i make a sample of the analog input? ie.  ones in every sampling time interval?
 
--Samik
             

好。
我将从现在开始发布模拟的屏幕截图。
当我设置增益时，SHDN应该处于高电平还是低电平状态？
我永久地将SHDN保持在地面潜力。



以下为原文

  Ok. I will post a screen shot of my simulation from now onwards. Should SHDN be in high or low state when i am setting my gain? i have kept SHDN at ground potential permanently.

除非您真的想将放大器置于关断模式，否则SHDN应该很低。
在
数据表中的一个应用图表显示该引脚刚刚接地。
所以很清楚
在你的情况下，没有必要让它变高。
重要的是要确保来自FPGA的信号真正发挥作用
这个设备。
如果你看一下引脚报告，所有这些信号应该与
Spartan 3AN入门套件参考指南中的引脚。
-  Gabor



以下为原文

SHDN should be low unless you really want to place the amplifier in shutdown mode.  In
the data sheet one application diagram shows this pin just grounded.  So there's clearly
no need to make it go high in your case.
 
The important thing is to make sure that your signals from the FPGA are really getting to
this device.  If you look at the pinout report, all of these signals should match with the
pins in the Spartan 3AN starter kit reference guide.
-- Gabor

以下是我在UCF中使用的ADC通信端口。（我已经跳过监视器通信引脚）
NET“system_clk”LOC =“E12”; NET“SPI_MOSI”LOC =“AB14”; NET“AMP_CS”LOC =“W6”; NET“SPI_SCK”LOC =“AA20”; NET“AD_CONV”LOC =“Y6”;
NET“data_from_adc”LOC =“D16”;
这些与数据表规范一致。
我还附上了填充Excel文档。
我可以看到端口已被指定为输出和输入但我不知道它们是否是正确的引脚！
再次感谢你！
--Samik



以下为原文

Here are the ADC communication ports i have used in the UCF.(i have skipped out the monitor communication pins)
 
NET "system_clk" LOC = "E12";
NET "SPI_MOSI" LOC = "AB14";
NET "AMP_CS" LOC = "W6";
NET "SPI_SCK" LOC = "AA20";
NET "AD_CONV" LOC = "Y6";
NET "data_from_adc" LOC = "D16";
 
These are consistent with the data-sheet specifications.
 
I am also attaching the pad Excel document. I can see that ports have been assigned as outputs and inputs but i have no idea whether they are the correct pins or not!
 
Thank You again!
 
--Samik

我在这里错过了SHDN引脚。
我今天会把这个引脚添加到这里然后再回复你。
但实际上Sayak的代码有关闭引脚约束，但我错过了它。
但是Sayak的代码也给出了同样的问题。
感谢您的帮助。
我将SHDN引脚用于它，然后用结果回复你。 
你能看到更多这些错误吗？
请告诉我，我也给了你引脚报告。
谢谢。
--Samik
adc_communication_test_pad.csv 21 KB



以下为原文

      I have missed the SHDN pin over here. I will add that pin over here today and get back to you. But actually Sayak's code had the shutdown pin constraint as well I missed it though. But then also Sayak's code gave the same problems. Thank You for your help. I will add the SHDN pin to it and get back to you with the results.
       Can you see more of these mistakes? Please let me know and I have given you the pinout report as well.
Thank You.
 
--Samik
            adc_communication_test_pad.csv ‏21 KB

没有SHDN引脚，我会期待你看到的失败。
其他事实
Sayak的代码中的错误导致类似的结果并不意味着改变这一点
引脚不会有所作为。
一般来说，我建议你在构建项目时下载到
董事会，你检查的地方＆amp;
“LOCED IOB”的路由报告，即
报告的顶部附近报告了其他用法。
这必须表明
100％或者你必须修复你的引脚限制。
请注意不正确的引脚
会造成伤害。
例如，你将AMP_SHDN驱动为低，但是如果
这不是找到的，那么你反而驱动一些随机引脚，
在您的情况下针脚C1。
如果C1碰巧连接到另一个驱动信号，这个
会导致驱动程序争用，可能会损坏FPGA或其他电路。
就个人而言，我认为应该有一个促进的“生产构建”选项
unlocated引脚错误，从而阻止你下载一个位文件
具有潜在破坏性随机引脚位置。
没有这样的选择，你需要
在下载到主板之前要小心检查报告。
-  Gabor



以下为原文

Without the SHDN pin, I would expect the failure you're seeing.  The fact that other
errors in Sayak's code caused a similar result does not mean that changing this
pin will not make a difference.
 
In general I would suggest that when you build a project to download to the
board, you check the place & route report for the "LOCed IOBs", which is
reported near the top of the report along with other usage.  This must show
100% or you must fix your pinout constraints.  Note that improper pinouts
can cause damage.  For example you are driving AMP_SHDN low, but if
this is not located, then you are instead driving some random pin low instead,
in your case pin C1.  If C1 happens to connect to another driven signal, this
can cause driver contention, possibly damaging the FPGA or other circuits.
 
Personally I think that there should be a "production build" option that promotes
unlocated pins to errors and thus prevents you from downloading a bit file that
has potentially damaging random pin locations.  Without such an option, you need
to be careful to check the reports before you download to the board.
-- Gabor

谢谢Gabor。
在将其上传到fpga之前，我们将确保没有错误的引脚。
我们能否相信电路板随附的数据表？
我问这个是因为我们已经发现了很多印刷错误。 
其次，我们已经添加了额外的AMP_SHDN引脚，我刚刚检查了布局和布线报告。
它显示100％。
设计总结报告：
外部IOB数量37个中的21个5％
外部输入IOB的数量2
外部输入IBUF数量2定位外部输入IBUF数量2中2个100％ 
外部输出IOB数量19
外部输出IOB数量19位置外部输出IOB数量19 19中的19％100％ 
我添加了SHDN。
代码没有任何问题，模拟工作正常。
但我仍然没有得到ADC的任何输出。 
事实上放大器不接受增益设置，与以前一样的问题！ 
我使用了相同的方法，即使用精细探针测量两条走线的输出电压，这两条走线从可编程放大器输出到ADC。 
以下是我得到的表格
VinA VinB放大器输出
0.78 0 0和3.35
0 0.78 0和1.67
0 0 0和1.67
2 0 0和0
0 2 0和1.67 
这些结果很奇怪。
增益已设置为-1（参考之前的模拟，它是相同的事情）。
你能解释一下Gabor吗？
“1.67”和“3.35”是放大器的参考和输入电压，但为什么它们出现在这里？ 
我们哪里出错了？
就外部信号而言，我使用电池（2节1.5伏电池和合适的分压电路）将电压信号提供给VinA和Vin B端口。
Vcc端口有3.3V，所以我不需要连接任何外部电压。
地面港口是我们供应的基础。
我需要连接除此之外的任何东西吗？
还有一件事，我的振幅设置在我上传程序后立即发生..在几纳秒内。
这个可以吗？
fpga是否需要有限的时间（大于几ns）才能正确设置。
我们缺少一些非常基本的东西吗
我们都是可编程硬件的新手。
谢谢
--Samik



以下为原文

          Thank you Gabor. We will make sure that there remains no wrong pin-outs before uploading it to the fpga. Can we trust the datasheet provided with the board for these? I am asking this because we have already found quite a few printing mistakes. 
           Secondly, we have added the extra AMP_SHDN pin out and I have just checked the place and route report. It shows 100% .
 
Design Summary Report:
Number of External IOBs 21 out of 372 5%
Number of External Input IOBs 2
Number of External Input IBUFs 2
Number of LOCed External Input IBUFs 2 out of 2 100%

Number of External Output IOBs 19
Number of External Output IOBs 19
Number of LOCed External Output IOBs 19 out of 19 100%
 
     I added the SHDN. There is nothing wrong with the code apparently, simulation works fine. But I am still NOT getting any output from the ADC.
 
     In fact the amplifier is not accepting the gain settings, the same problem as before! 
 
     I have used the same methodology, ie, used a fine probe to measure the output voltages from the two traces that make their way out from the programmable amplifier and into the ADC. 
    The following is a tabulation of what I got
 
VinA        VinB       amplifier output
0.78         0                0 and 3.35
0               0.78          0 and 1.67
0               0               0 and 1.67
2               0               0 and 0
0               2               0 and 1.67
 
       These results are pretty strange. The gain has been set to -1 (refer to the previous simulation, it is the same thing).
Can you explain these Gabor?
 
"1.67" and "3.35" are the reference and input voltages to the amplifier, but why are they appearing over here?? 
 
       Where are we going wrong? As far as external signals are concerned I am using a battery (2 batteries of 1.5 V and suitable potential divider circuits) to give the voltage signals to the VinA and Vin B ports. And the Vcc port has 3.3V so I need not attach any external voltage to it. And the ground port is the ground of our supply. Do I need to connect anything more than these?
 
One more thing, my amplitude setting occurs immediately after I upload my program.. Within a few nanoseconds. Is this OK? Does the fpga need a finite amount of time (greater than a few ns) to properly set up.
 
Are we missing something very basic? We are all new to programmable hardware.
 
Thank You
 
--Samik
 
     
 
 

没有走出“范围并观察SPI信号，很难猜出是什么
可能会发生。
某些东西可能会干扰写入
放大器，但这是否是由启动后立即执行或
从别的东西很难说。
从理论上讲，它应该很容易改变
你的代码，它定期写入增益寄存器，而不是
启动后只需一次。
或者你可以在启动后使用计数器添加一个很长的延迟。
如果你有ChipScope的另一种可能性就是使用它来连接ChipScope
ChipScope核心插入器。
然后你就像逻辑分析器那样
可以向您展示FPGA的内部信号在硬件中的作用。
关于ChipScope的一个警示：您无法立即看到发生了什么
在配置FPGA之后，您需要添加一个非常长的延迟（几秒钟）
下载位文件后给自己一些时间来设置触发器。
然而，对于您的设置，我认为真正的示波器或逻辑分析仪将是一个
更好的工具使用。
至于文档中的错误，您有两个地方可以引用用户
指南。
一个是电路板原理图，另一个是随附的.ucf文件
参考设计。
这两个都应该有正确的引脚排列。
有
第75页的用户指南中的.ucf文件片段，如图9-5所示。
我理解了
它具有与报告的不同的IOSTANDARD和DRIVE属性集
为您的设计。
虽然这不太可能是一个问题，但它可能是可能的
需要较低的驱动强度以避免过冲或下冲
SPI_SCK信号。
如果您不在.ucf文件中提供IOSTANDARD或DRIVE或SLEW会发生什么
是你获得所有默认设置。
我相信斯巴达3将是2.5V
LVCMOS，12 mA驱动，慢速摆动。
由于信号实际上在银行
使用3.3V Vcco电源，你并没有真正获得2.5V LVCMOS，而是因为这些工具
被告知你有2.5V它会导致你的驱动强度甚至更大
工具报告的12 mA电流。
所以这应该是固定的，即使它不太可能
成为你的主要问题。
-  Gabor



以下为原文

Without getting out a 'scope and looking at the SPI signals, it's hard to guess what
might be happening.  It is possible that something is interfering with the writes to
the amplifier, but whether that's caused by doing it immediately after startup or
from something else is hard to say.  Theoretically it should be easy to change
your code such that it writes to the gain register at regular intervals instead of
just once after startup.  Or you could add a long delay after startup using a counter.
 
Another possibility if you have ChipScope is to hook up ChipScope using the
ChipScope core inserter.  Then you have something like a logic analyzer that
can show you what the internal signals of the FPGA are really doing in hardware.
One cautionary word about ChipScope:  You can't really see what goes on immediately
after configuring the FPGA, so you'd need to add a really long delay (several seconds)
to give yourself time to arm the trigger after downloading your bit file.
 
However for your setup I would think a real oscilloscope or logic analyzer would be a
better tool to use.
 
As for errors in the documents, you have two places to reference against the user
guide.  One is the board schematics, and the other is the .ucf file that goes with
the reference designs.  Both of these should have the correct pinout.  There is
a snippet of the .ucf file in the user guide on page 75, figure 9-5.  I can see that
it has a different set of IOSTANDARD and DRIVE attributes than what was reported
for your design.  Although that's not as likely to be an issue, it could be possible
that the lower drive strength is required to avoid overshoot or undershoot on the
SPI_SCK signal.
 
What happens if you don't supply IOSTANDARD or DRIVE or SLEW in your .ucf file
is that you get all of the default settings.  I believe for Spartan 3 that will be 2.5V
LVCMOS, 12 mA drive, and slow slew.  Since the signals are actually on a bank
with a 3.3V Vcco supply, you don't really get 2.5V LVCMOS, but because the tools
were told that you had 2.5V it causes your drive strength to be even larger than
the 12 mA reported by the tools.  So that should be fixed, even if it's not likely
to be your main problem.
-- Gabor

正如你所指出的，我们正在考虑在启动和修改iostandards，slews和驱动器后给出更长的延迟。
我们也有示波器供我们使用。
我们究竟需要检查什么以及如何检查？
你的意思是说我们应该注意前置放大器在SPI引脚接收的信号波形吗？
谢谢，
Sayak。



以下为原文

We are thinking of giving a longer delay after start up and modifying the iostandards, slews and drives as u pointed out. Also we have oscilloscopes at our disposal. What exactly do we need to check and how? U mean to say we should note the waveforms of the signal the preamplifier is receiving at the SPI pin?
 
Thanks,
Sayak.

你当然可以从检查放大器SPI接口的信号开始。
这会告诉你是否有一些董事会级别的问题阻止你的程序
到达寄存器。
如果您更改了代码，那么这将更容易
写入放大器定期发生，而不是只发生一次。
否则你需要
重新加载FPGA以获得'范围内的每个新样本。
-  Gabor



以下为原文

You could certainly start by checking the signals going to the SPI interface of the amplifier.
That would tell you if there is some board-level issue preventing your program from
reaching the registers.  This would be easier if you changed your code so that the
write to tha amplifier happens periodically instead of just once.  Otherwise you'd need
to reload the FPGA to get each new sample on the 'scope.
-- Gabor

你发现我们的AD_CONV信号有什么问题吗？
仿真表明，everthing是正确的并且满足最小约束条件。
但我们测量了ADC AD_CONV引脚的电压，发现恒定电压为3.35，即Vcc电压。
我们哪里出错了？
你能看看我们的代码，特别是我们定义AD_CONV信号的部分吗？
你发现错了吗？
--Samik



以下为原文

Do you find anything wrong with our AD_CONV signal? The simulation shows everthing to be correct and satisfying the minimum constraints. But we measured the voltage at the AD_CONV pin of the ADC and found a constant voltage of 3.35 which is the Vcc voltage. Where are we going wrong? Can you just have a look at our code, especially the part where we have defined the AD_CONV signal? Do you find something wrong?
 
--Samik

看看这一行： 
ad_conv_tempafter 100 ns;
--data sheet给出ad_conv的最小宽度为4 ns
基于时间的延迟不可综合。
所以第一次发表此声明
到达时，ad_conv_temp变为'1'并永远保持'1'。
如果这也可以看出
你运行翻译后模拟。
您需要对此进行编码，以便ad_conv_temp在经过一些修改后返回到零
时钟周期。
例如，如果你想要五个时钟，你可以把它变低
conv_count变为5像： 
如果rising_edge（system_clk）那么如果conv_count = 1302那么ad_conv_temp--，'0'在100 ns之后;
--data sheet给出ad_conv的最小宽度为4 ns conv_count：= 0;
elsif conv_count = 5然后ad_conv_temp结束if;
conv_count：= conv_count + 1;
万一;
[编辑] 
看一下翻译后的模拟，看来你还有一些这样的延迟
时间来修复。
其中SHDN引脚始终为高电平，并且没有足够的延迟
从amp_cs的断言（低电平边沿）到spi_sck的上升沿。
-  Gabor



以下为原文

Look at this line:
 
         ad_conv_temp<='1', '0' after 100 ns;   --data sheet gives min width of ad_conv as 4 ns



Time-based delays are not synthesizable.  So in effect the first time this statement
is reached, ad_conv_temp becomes '1' and stays '1' forever.  This can also be seen if
you run post-translate simulation.
 
You need to code this so ad_conv_temp goes back to zero after some number of
clock cycles.  For example if you wanted five clocks, you could have it go low when
conv_count becomes 5 like:
 
  if rising_edge(system_clk) then
      if conv_count=1302 then
         ad_conv_temp<='1'; --, '0' after 100 ns;   --data sheet gives min width of ad_conv as 4 ns
        conv_count:=0;
      elsif conv_count = 5 then
         ad_conv_temp<='0';
      end if;
    conv_count:=conv_count+1;
  end if;


[Edit]
  Looking at the post-translate simulation, it seems you have a few more of these delay
times to fix.  Among them the SHDN pin is always high, and there is not enough delay
from the assertion (low-going edge) of amp_cs to the rising edge of spi_sck.
-- Gabor