如何让Spartan 3AN支持实例化LVDS发送器？

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以下为原文

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krisverbeeck写道：
我有点困惑（已经有一段时间我一直在研究XIlinx部件;）。
我想实例化一个LVDS发送器，打开核心生成器，转到SelectIO接口向导......但发现Spartan 3AN不支持它？
是什么赋予了？
更重要的是，我该如何解决这个问题呢？
无需使用Core Generator。
打开S3AN的HDL库指南。
复制实例化模板。
----------------------------是的，我这样做是为了谋生。



以下为原文

krisverbeeck wrote:
I'm a bit confused (and it's been a while I've been working on XIlinx parts ;). I'd like to instantiate an LVDS transmitter, opened the Core Generator, went to the SelectIO Interface Wizard... only to find it is not supported on Spartan 3AN? What gives? And more importantly, how do I get around this?
 
 

No need to use the Core Generator.
 
Open up the HDL Library Guide for S3AN. Copy the instantiation template.
----------------------------Yes, I do this for a living.

好吧，我能找到的是如何实例化OBUFDS，这很好但不是我想要的。
实际上，SelectIO正是我想要的。
只有不是斯巴达3AN。
不明白为什么它不受支持。
对我毫无意义。
还找到了7：1或1：7发射器和接收器的设计实例/应用笔记，但又一次：不是我想要的。
需要1：8。
无法想象为什么这不是更直接的。
在2002年的Altera软件中有一个向导...



以下为原文

Well, all I can find is how to instantiate OBUFDS, which is nice but not what I was looking for. Actually, the SelectIO is exactly what I am looking for. Only not for the Spartan 3AN. Don't understand why it's not supported. Makes no sense to me.
 
Also found a design example/app note for 7:1 or 1:7 transmitters and receivers but again: not what I was looking for. Need 1:8.
 
Can't imagine why this is not more straight forward. There was a wizard for this in Altera soft in 2002...

我不太确定为什么“SelectIO”在Spartan-II和Spartan-6中，但是3错过了！
不要太担心它 - 它只是一个营销术语！
OBUFDS是您需要的基本构建块。
8：1或1：8应该比7：1容易实现，因为传输时钟将是系统时钟的很好的整数倍。
您可以使用XAPP486获得灵感，但它可以像系统时钟一样简单，DCM可以生成频率为4倍的时钟，FIFO和DDR输出触发器。
我没有使用Altera部件，所以我不确定他们的向导有多好，但即使你确实可以访问SelectIO核心生成器，例如在Spartan-6上，你会发现它生成的代码是
仅仅是自定义修改的起点，对于相当简单的任务，从头开始编写代码可能更容易（至少在您第一次执行此操作时）。



以下为原文

I'm not quite sure why "SelectIO" is in the Spartan-II and Spartan-6 but the 3 missed out! Don't worry too much about it - it's just a marketing term!
 
OBUFDS is the basic building block you'll need. 8:1 or 1:8 should be a lot easier to implement than 7:1 since the transmit  clock will be a nice integer multiple of the system clock. You can probably use XAPP486 for inspiration, but it could be as simple as a system clock, a DCM to generate a clock of 4 times the frequency, a FIFO, and the DDR output flip flops.
 
I haven't used Altera parts so I'm not sure how good their wizards are, but even if you did have access to the SelectIO core generator, on the Spartan-6 for example, you will often find that the code it generates is merely a starting point for custom modifications, and for reasonably straightforward tasks it might be easier to code things from scratch (at least the very first time you have to do it).
 

krisverbeeck写道：
好吧，我能找到的是如何实例化OBUFDS，这很好但不是我想要的。
实际上，SelectIO正是我想要的。
只有不是斯巴达3AN。
不明白为什么它不受支持。
对我毫无意义。
OBUFDS只是输出缓冲器，它允许您使用差分IOSTANDARD将信号驱出FPGA。
是的，它是SelectIO的一部分，在S3中不包括S6和Virtex设备的OSERDES和ISERDES。
因此，如果您需要进行任何类型的序列化，反序列化，则需要使用结构触发器进行，而不是在IOB中进行。
这是非常好的 - 我一直这样做 - 但是你不会得到S6和Virtex部件的超级快速速率，因为S3 FPGA根本无法快速计时。
还找到了7：1或1：7发射器和接收器的设计实例/应用笔记，但又一次：不是我想要的。
需要1：8。
不要在7：1和1：7序列化/反序列化的应用笔记上浪费你的时间。
它很好地总结了Xilinx应用笔记中的所有错误。
未注释的代码，原始实例化，与代码不匹配的文本和图表，一切。
在FPGA中执行1：8反序列化非常容易。
除非您需要速度，否则它不需要SERDES块。
数据流是否伴有帧信号？
如果没有，则必须嵌入成帧信息，并且必须执行“bitlip”状态机以确定何时捕获传入数据。
无法想象为什么这不是更直接的。
在2002年的Altera软件中有一个向导...
因为它很简单，你不需要向导。
在一张方格纸上画出你如何反序列化。
真的，这并不难。
----------------------------是的，我这样做是为了谋生。



以下为原文

krisverbeeck wrote:
Well, all I can find is how to instantiate OBUFDS, which is nice but not what I was looking for. Actually, the SelectIO is exactly what I am looking for. Only not for the Spartan 3AN. Don't understand why it's not supported. Makes no sense to me.
 
 
OBUFDS is only the output buffer, which is what allows you to drive your signal out of the FPGA using a differential IOSTANDARD. Yes, it's part of SelectIO, which in S3 doesn't include the OSERDES and ISERDES of S6 and Virtex devices. So if you need to do any kind of serialization, deserialization, you need to do it using fabric flops, not in the IOB. Which is perfectly fine -- I do this all the time -- but you won't get the super-duper fast rates you get with S6 and Virtex parts because the S3 FPGA simply can't clock that fast.
 
Also found a design example/app note for 7:1 or 1:7 transmitters and receivers but again: not what I was looking for. Need 1:8.
 
 
DO NOT waste your time on that app note for 7:1 and 1:7 serialization/deserialization. It nicely sums up everything that is WRONG with Xilinx app notes. Uncommented code, primitive instantiations, text and diagrams that don't match the code, everything.
 
Doing 1:8 deserialization in an FPGA is EASY. It doesn't need a SERDES block unless you have a need for speed.
 
Is the data stream accompanied by a framing signal? If not, then it has to have framing information embedded and you have to do a "bitslip" state machine to determine when to capture the incoming data.
 
Can't imagine why this is not more straight forward. There was a wizard for this in Altera soft in 2002...

Because it's easy and you don't need a wizard. Draw out on a sheet of graph paper how you'd deserialize. Really, it's not hard.
----------------------------Yes, I do this for a living.