如何使用PSoC实现并行到串行转换

对于并行到串行转换和返回，不需要XTRA硬件。
考虑使用移位寄存器（8, 16, 24或32位宽）。你移出一个串行数据流，你可以转换到另一个移位寄存器，现在接收一个平行字的所需大小再次。
另一种解决方案可以采用多路复用器和阿德多路复用器，在串行化硬件信号时，背靠背工作得相当好。
最后一个解决方案是在CPU的帮助下进行串行化，但该方法将耗费MIPS。
鲍勃



     以下为原文
  There is no xtra hardware needed for a parallel - to serial conversion and back.
    Consider to use a shift register (8, 16, 24 or 32 bits - wide). You shift out a serial datastream which you may shift into another shift register receiving now a parallel word of the desired size again.
     
    Another solution could be made with a multiplexer and a de-multiplexer connected back-to-back working pretty well when serializing hardware signals.
     
    Last solution is serializing with the help of the CPU but that method will cost you MIPS.
     
    Bob

甚至LUTS都可以使用……但值得关注的是有一个专门的组件，它仅仅是为了移动数据而建立的……
当使用这样一个经过验证、测试和认可的组件时，我怀疑是否有人会考虑把时间花在重新发明车轮上。
无论什么。。。我不知道我的实现是正确的还是错误的……如果你们中的任何一个都能正确地处理这个组件（我正在谈论的是串行地转换数据），那么请在CRO中附加项目和屏幕截图（包含时钟和串行输出）。



     以下为原文
   Even LUTs can be used.....but the concern is there is a dedicated component which is solely built for shifting data..........
    When such a verified, tested and approved component is used I doubt anyone will think on investing their time on reinventing the wheel.
    Whatever... i dont know whether my implementation was right or wrong.......If any of you get to work the component right (I am talking about shifting data serially out) then please do attach the project as well as screen shot in CRO (containing clock and serial out)

移位复合物实际上就是你所需要的。如果你能在一个简单的项目中描述你所描述的问题（不涉及任何其他事情），它编译时没有任何警告（特别是从STA关于时间），你应该用CyPress来提交一个支持案例。
当你说Shift组件在加载并行值时，时钟会显示出第一个比特，你的意思是什么时刻？是用API编写的，还是使用加载输入将它加载到寄存器本身时呢？对于后一种情况，数据表表示，当负载变高时，时钟发生的时刻也很高。这会是你的问题吗？



     以下为原文
  The shift compoent is actually what you need. If you can show the problem you describe in a simple project (not involving anything else), which compiles without any warnings (esp. from STA regarding timing), you should file a support case with Cypress.
    When you say the shift component clocks out the first bit when you load the parallel value - what exact moment do you mean? Is it when you write it with the API, or when you use the LOAD input to load it into the register itself? For the latter one, the data sheet says it happens the exact moment when, after LOAD went high, the clock also wents high. Could this be your problem?

我正在使用ApvestHeaveGrWordRealEgValueMe（）将值写入SHIVTRAG中，稍后我将左移数据。
这里是我的代码功能
停止移位寄存器（数据表称应该停止组件使用API SHIVTERGGWORKRIER EGEVALUE）
使用API SHIVTERGGWORKEGRIGEVALUE（）
启动移位寄存器
在for循环提供8个时钟来转移所有的位…
我注意到的是，第一次，我必须提供8个时钟组件，以获得所有8位，但第二次和随之而来的时间，我只需要提供7个时钟，以获得所有的位，因为第一位已经出来之前，甚至给时钟…
问题是什么？？？？？？？？



     以下为原文
   I am writing value into the shiftreg using the API Shiftreg_WriteRegValue() and I am left shifting the data later on
    So here is my code functionality
    Stop Shift register(data sheet says component should be stopped to use the API Shiftreg_WriteRegValue)
    Use the API Shiftreg_WriteRegValue()
    Start the Shift register
    In the for loop provide 8 clocks to shift all the bits out.....
    What I noticed was for the first time I had to provide 8 clocks to component to get all the 8 bits out, but for second and consequent times I just had to provide 7 clocks to get all bits out because first bit was already out before even giving the clock.........
    What is the problem??????

因此，这看起来像是路由/优化步骤中的一个错误。然后在Shiftreg和CRC之间添加一个同步组件可能会有所帮助。哪里有STA的警告？



     以下为原文
  So this looks like a bug in the routing / optimization step. Then maybe adding a sync component between Shiftreg and CRC might help. Where there any warnings from the STA?

我们使用移位寄存器有类似的问题，但我能记得它到底是什么，我们使用我们自己的换档例程由于项目Shdulle，并计划再次检查，如果我们有时间。大家都知道，那一刻永远不会到来。我认为你应该为柏树提供一个案例。



     以下为原文
  We have similar problem using the shift register but I can remember what exactly it was, we used our own shift routine due to the project schdule and was planning to check that again if we have the time. As everybody knows, that time never come. I think you should issue a case for Cypress support.

我认为柏树员工应该能够解决这个问题……



     以下为原文
   I think Cypress employees should be able to solve this problem......

我张贴的项目包括：并行到串行和后退。
今晚我有主意不使用移位寄存器，但是UART也可以使用。
鲍勃



     以下为原文
  The project I posted contains both: parallel to serial and back.
    Tonight I had the idea not to use a shift-register but an UART which will work as well
     
    Bob