使用外部3.3v同时驱动Vreg和Vdd是否还需要40uf Vreg电容

你好，Iurie，
 
 
1.如果我使用外部3.3v同时驱动Vreg和Vdd（禁用内部寄存器），我是否还需要40uf Vreg电容或我只能使用一个10uf？
在这种情况下，您可以使用22uF电容（VDD输入需要10uF，逻辑电源需要额外一些）。如果使用电解电容，则需要在VREG和VDD引脚旁边添加一个100nF陶瓷电容。
 
2.我可以使用Vs大容量电容器，但爱人价值更高但ESR更好吗？ ESR和纹波电流是Vs体积电容的主要参数，对吗？
这种说法适用于滤除PWM工作所需电流脉冲的陶瓷电容器。在建议的布局中，您应该在VSA引脚附近放置一个100nF陶瓷帽，在VSB引脚附近放置一个100nF陶瓷帽。
大容量电容器更大，可以具有更高的ERS。其功能是在负载变化期间向系统提供电荷（例如，当您从保持切换到加速电流时）。它应根据最大负载电流变化和主电源与主体之间的寄生电感来确定大小。
安装在EVAL6470H电路板上的100uF尺寸考虑了最差条件（通过需要强负载变化的长电线供电），但您可以根据实际应用降低此值。
 
3.当外部Vreg = Vdd = 3.3v时，SW引脚是否仍能耐受5v？
是的。但请注意，SW输入上拉至VDD。如果在这种情况下对引脚施加5V电压，则会向3.3电源提供电流。
 
问候
恩里科



以下为原文





Hello Iurie,


1. If I use an external 3.3v to drive both Vreg and Vdd (internal reg disabled), do I still need a 40uf Vreg cap or I can use just one 10uf?
In this case you could use a 22uF capacitor (the 10uF required by VDD input + some extra for the logic supply). If an electrolytic cap is used, you need to add a 100nF ceramic capacitor next to VREG and VDD pins.

2. Can I use Vs bulk capacitor with lover value but better ESR? ESR and Ripple current is primary parameters for Vs bulk cap, am I right?
This statement is true for the ceramic capacitors filtering the current pulses required by PWM operation. In the suggested layout you should place a 100nF ceramic cap near VSA pins and a 100nF ceramic cap near VSB pins.
The bulk capacitor is bigger and it can have higher ERS. Its function is to supply the charge to the system during load variations (e.g. when you switch from holding to acceleration current). It should be sized according to the maximum load current variation and the parasitic inductance between the main power source and bulk.
The 100uF mounted on EVAL6470H boards is sized considering worst conditions (you supply the board through long wires requiring strong load variations), but you could reduce this value according to your real application.

3. Is the SW pin still 5v tolerant when external Vreg = Vdd = 3.3v?
Yes, it is. But please note that the SW input is pull-upped to VDD. If you apply 5V to the pin in this condition a current is sourced to your 3.3 supply.

Regards
Enrico

谢谢你的回答，恩里科。
 
我正试图节省电路板空间。我有3 x L6470并排紧密排列，宽度约为60mm。每个通道最大1.5安培RMS电流。所有Vsa V***引脚都将通过引脚附近的小陶瓷0.1uf电容去耦。
我可以使用单个大容量上限进行此类多渠道应用吗？
 
Iurie



以下为原文





Thanks for the answers, Enrico.

I'm trying to save the board space. I have 3 x L6470 tightly spaced side by side with each other in about 60mm width. 1.5 Amp RMS current for each channel maximum. All Vsa V*** pins will be decoupled with a small ceramic 0.1uf caps near pins.      
Can I use single bulk cap for such multichannel application?  

Iurie

是的，在这种情况下，我认为您可以在整个应用中使用单个100uF大容量电容。
 
亲切的问候
恩里科



以下为原文





Yes, in this case I think you can use a single 100uF bulk capacitor for the whole application.

Kind Regards
Enrico