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我使用VHDL在FPGA上创建了一个音箱。
它有3个按钮和3个选择开关。 当任何选择器开关为高“1”时,与该开关相连的音调会在其为高电平时播放。 当它变低时,音调停止。 我希望我的按钮在切换为高'1'时,在按钮释放后保持高电平3秒,然后转到零。 有人称这是一次性,其中一个循环锁定一点。 我试图使用等待声明,但它不起作用。 只要按住按钮,音调就会播放,但在释放时会立即停止。 这是我的代码的一部分。 任何帮助表示赞赏。 注意:周期是一个常数(即'恒定周期:时间:= 1000毫秒;') D1:如果btn_a ='1'则进程开始,然后tempdata等待3 *周期; elsif btn_b ='1'然后tempdata等待3 *期; elsif btn_c ='1'然后tempdata等待3 *期; elsif swt_a ='1'然后tempdata等到swt_a ='0'; elsif swt_b ='1'然后tempdata等到swt_b ='0'; elsif swt_c ='1'然后tempdata等到swt_c ='0'; 结束如果;结束过程; dataout 以下为原文 I have created a sound box on my FPGA using VHDL. It has 3 push buttons ans 3 selector switches. When any selector switch is high '1' the tone tied to that switch plays as long as it is high. When it goes low the tone stops. I would like my buttons, when switched high '1', to stay high for 3 second after the button is released, then go to zero. Some call this a one-shot, where a single cycle latches a bit. I am trying to use a wait statement, but it is not working. The tone plays as long as I hold the button, but stops immediately when released. Here is a section of my code. Any help is appreciated. NOTE: period is a constant (i.e. 'constant period: time := 1000ms;') D1: process begin if btn_a = '1' then tempdata <= squareout; wait for 3 * period; elsif btn_b = '1' then tempdata <= integerout; wait for 3 * period; elsif btn_c = '1' then tempdata <= ipcoreout; wait for 3 * period; elsif swt_a = '1' then tempdata <= squareout; wait until swt_a = '0'; elsif swt_b = '1' then tempdata <= integerout; wait until swt_b = '0'; elsif swt_c = '1' then tempdata <= ipcoreout; wait until swt_c = '0'; end if; end process; dataout <= tempdata; |
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4个回答
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嗨@ rblackmon002,
合成工具通常不支持类型TIME,因此vivado不支持它(ref UG901 p198): 您需要了解的事实是,VHDL的很大一部分仅用于仿真,不适用于综合和真实硬件。 如果你想等待3秒,有两个解决方案: - >使用微填充软件在软件中执行此操作 - >在HW中,您应该知道clk的频率。 使用计数器计算时钟边沿的数量为3秒。 亲切的问候, 弗洛朗 FlorentProduct应用工程师 - Xilinx技术支持EMEA ------------------------------------------ -------------------------------------------------- ----------------------------不要忘记回复,kudo,并接受作为解决方案。 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Hi @rblackmon002, Type TIME is usually not supported by synthesis tool so it is not supported by vivado (ref UG901 p198): You need to be awawe of the fact that a big part of VHDL is only for simulation and is not applicable for synthesis and real hardware. If you want to wait for 3 sec, there are two solution: -> use a microblaze to do it in Software -> In HW, You should know the frequency of your clk. Use a counter to count the number of clock edges to do 3sec. Kind Regards, Florent Florent Product Application Engineer - Xilinx Technical Support EMEA ------------------------------------------------------------------------------------------------------------------------ Don't forget to reply, kudo, and accept as solution. View solution in original post |
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嗨@ rblackmon002,
合成工具通常不支持类型TIME,因此vivado不支持它(ref UG901 p198): 您需要了解的事实是,VHDL的很大一部分仅用于仿真,不适用于综合和真实硬件。 如果你想等待3秒,有两个解决方案: - >使用微填充软件在软件中执行此操作 - >在HW中,您应该知道clk的频率。 使用计数器计算时钟边沿的数量为3秒。 亲切的问候, 弗洛朗 FlorentProduct应用工程师 - Xilinx技术支持EMEA ------------------------------------------ -------------------------------------------------- ----------------------------不要忘记回复,kudo,并接受作为解决方案。 以上来自于谷歌翻译 以下为原文 Hi @rblackmon002, Type TIME is usually not supported by synthesis tool so it is not supported by vivado (ref UG901 p198): You need to be awawe of the fact that a big part of VHDL is only for simulation and is not applicable for synthesis and real hardware. If you want to wait for 3 sec, there are two solution: -> use a microblaze to do it in Software -> In HW, You should know the frequency of your clk. Use a counter to count the number of clock edges to do 3sec. Kind Regards, Florent Florent Product Application Engineer - Xilinx Technical Support EMEA ------------------------------------------------------------------------------------------------------------------------ Don't forget to reply, kudo, and accept as solution. |
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“等待”是不可综合的。
在硬件中产生显着延迟的唯一方法是使用单独的计数器(从某个时钟源运行)并等到该计数器达到某个值然后再继续。 以上来自于谷歌翻译 以下为原文 "wait" is not synthesizable. The only way to create a significant delay in hardware is to have a separate counter (running from some clock source) and wait until that counter reaches a certain value before continuing. |
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我用了一个柜台。
它花了几次迭代,但效果很好。 谢谢 这是代码,如果有人有兴趣... P1:进程(clk,rst,btn_a,on_a)如果rst ='1'并且btn_a ='0'则开始,然后on_a elsif rst ='0'并且btn_a ='1'然后是cntra'0'); on_a elsif(rising_edge(clk)和on_a ='1')然后cntra如果cntra on_a else on_a结束if; 结束如果;结束过程; 以上来自于谷歌翻译 以下为原文 I used a counter. It took a few iterations, but it worked great. Thanks Here is the code, if anyone is interested... P1: process(clk, rst, btn_a, on_a) begin if rst = '1' and btn_a = '0' then on_a <= '0'; elsif rst = '0' and btn_a = '1' then cntra <= (others => '0'); on_a <= '1'; elsif (rising_edge(clk) and on_a = '1') then cntra <= cntra +1; if cntra < 200000000 then on_a <= '1'; else on_a <= '0'; end if; end if; end process; |
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