PSoC 3待中断

我注意到在我的PSoC 3 ES3和AM试图理解它的中断行为。
我有一个边缘触发ISR组件连接到一个数字线路（我将称之为ISR1）。
给出以下顺序：
从上电（中断使能位isr1和全局中断不是默认设置）中断源时，设置挂起的国旗isr1叫isr1_start()；电话isr1_stop()；电话isr1_clearpending()；打电话时cyglobalintenable cyglobalintenable称，为isr1 ISR是我中等执行。检查intc_clr_en和intc_clr_pd登记确认isr1不启用或等候时，全局中断使能。
我想中断未决或中断控制器或CPU的某个地方，但我一直在阅读时间不能确定，这是悬而未决或如何清除它。任何对此的洞察都是值得赞赏的。
注：我可以99%通过移动clearpending开始之前解决问题，所以isr1未启用和未决的同时。但这不是一个真正的解决方案，有一个小机会的中断可能会触发启动和停止期间。另外，我想了解到底发生了什么。
谢谢，
——乔纳森



     以下为原文
   I have noticed the following interrupt behavior on my PSoC 3 ES3 and am trying to understand it.
    I have an edge triggered ISR component connected to a digital line (I'll call it ISR1).
    Given the following sequence:
   

     
• Starting at power up (interrupt enable bit for ISR1 and global interrupt are not set by default)
• Interrupt source occurs, setting the pending flag for ISR1
• Call ISR1_Start();
• Call ISR1_Stop();
• Call ISR1_ClearPending();
• Call CyGlobalIntEnable
  

    When CyGlobalIntEnable is called, the isr for ISR1 is immediately executed. Checking the INTC_CLR_EN and INTC_CLR_PD registers confirms that ISR1 is neither enabled nor pending when global interrupts are enabled.
    I assume the interrupt is pending somewhere in either the interrupt controller or CPU, but I have been reading the TRM and cannot determine where it is pending or how to clear it. Any insight on this is appreciated.
    Note: I can 99% solve the problem by moving the ClearPending before the Start, so ISR1 is not enabled and pending at the same time. But this is not really a solution as there is a small chance the interrupt could be triggered during the period between Start and Stop. Plus I would like to understand what is actually happening.
    Thanks,
    -- Jonathan