脉冲宽度代码如何在vhdl中查看

如果您尝试合成此代码，将会遇到很多错误。
尝试用简单的同步方法来思考
countnrs和D触发器。
不要在任何不是“时钟”的事件上使用'event关键字。
所以
如果你想在输入脉冲上看到一个事件，请运行它
2 D触发器并检查是否有那些触发器的输出
比赛。
注意：甚至不要只考虑使用一个触发器
并将其与输入信号进行比较！
生成“事件”
用这种方法不能保证工作，因为
输入与时钟不同步，所以时间
输入改变，直到下一个时钟边沿无法计数
超过任何有用的延迟时间。
这是一个同步过程：
test_counter_a_pw：process（clk_50mhz） - 同步进程仅依赖于时钟edgebeginif clk_50mhz'event和clk_50mhz ='1'然后 - 同步进程，时钟边缘为外“if”如果a_count_rst ='1'那么 - 这现在是
同步复位a_count_pw a_count_pw_reported否则J3_IO1_q J3_IO1_qq如果J3_IO1_qq ='0'且J3_IO1_q ='1'则 - 检测上升沿a_count_pw elsif J3_IO1_qq ='1'且J3_IO1_q ='0'然后 - 检测下降沿a_count_pw_reported否则a_count_pw结束如果结束
if; end process test_counter_a_pw;
-  Gabor
-  Gabor
在原帖中查看解决方案



以下为原文

You're going to get lots of errors if you try to synthesize this code.
Try to think in terms of what you can do with simple synchronous
countnrs and D flip-flops.
 
Don't use the 'event keyword on anything that's not "the" clock.  So
if you want to see an event on the input pulse, run it through
2 D flip-flops and check to see whether the output of those flops
match.  NOTE:  Don't even think of using just one flip-flop
and comparing it to the input signal!  The "event" generated
with this approach is not guaranteed to work because the
input is not synchronous to the clock, so the time when
the input changes until the next clock edge cannot be counted
on to be more than any useful delay time.
 
Here's a synchronous process:
 
test_counter_a_pw: process(clk_50mhz) -- Synchronous process depends ONLY on clock edge
begin
 if clk_50mhz'event and clk_50mhz='1' then -- Synchronous process, clock edge is outer "if"
  if a_count_rst='1' then -- this is now a synchronous reset
   a_count_pw <= X"00000000";
   a_count_pw_reported <= a_count_pw_reported; -- This line is now superfluous, anything not explicitly changed keeps its value in VHDL
  else
   J3_IO1_q <= J3_IO1;  -- First D FF stage (common synchronization point)
   J3_IO1_qq <= J3_IO1_q; -- Second D FF stage for edge detect
   if  J3_IO1_qq = '0' and J3_IO1_q = '1' then -- Detect rising edge
     a_count_pw <= X"00000000"; -- Start from 0 at rising edge
   elsif J3_IO1_qq = '1' and J3_IO1_q = '0' then -- Detect falling edge
     a_count_pw_reported <= a_count_pw;  -- Capture count
   else
     a_count_pw <= a_count_pw + 1;
   end if
  end if;
end process test_counter_a_pw;


-- Gabor

-- GaborView solution in original post

在伪代码中，用于测量脉冲宽度的简单状态机器将类似于：
1.等待脉冲前沿，保持计数器复位
2.脉冲开始，让计数器递增，直到检测到脉冲后沿
3.脉冲结束，冻结计数器（或拍摄计数器值的快照）
4.循环回状态＃1
你可以毫不费力地结合其中一些状态。
将此伪代码转换为VHDL应该非常简单。
（Verilog会更容易，当然:)）
确保在脉冲到达状态机或计数器附近的任何位置之前将脉冲与50MHz时钟同步。
确保计数器足够宽以处理尽可能长的脉冲宽度，或添加“溢出”检测的规定。
这是你在寻找什么？
我不知道PRI / PRF是什么意思。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

In pseudo code, a simple state machiine to measure pulse width would look something like:
 
1.  waiting for leading edge of pulse, keep counter reset
2.  pulse started, let counter increment until pulse trailing edge detected
3.  pulse ended, freeze counter (or take a snapshot of counter value)
4.  loop back to state #1
 
You can combine some of these states without much trouble.
Converting this pseudo-code to VHDL should be pretty simple. (Verilog would be even easier, of course  :)  )
Make sure you synchronise the pulse to the 50MHz clock before it goes anywhere near your state machine or counters.
Make sure your counter is wide enough to handle the longest possible pulse width, or add a provision for "overflow" detection.
 
Is this what you were looking for?  I have no idea what PRI/PRF means.
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

是的，这与我正在寻找的是一致的。
我有以下代码，我生成的提示。
我有一个J3_IO1的输入信号，它有一个计数器a_count_pw，并在clk_50mhz时基于J3_IO1递增。
要保存该值，我将其保存在a_count_pw_reported中。
我接近长路的正确道路吗？
test_counter_a_pw：进程（J3_IO1，a_count_rst，clk_50mhz）开始，如果a_count_rst ='1'则a_count_pw a_count_pw_reported elsif clk_50mhz'event和clk_50mhz ='1'然后如果J3_IO1'event和J3_IO1 ='1'则a_count_pw否则a_count_pw a_count_pw_reported结束if;
万一;
结束过程test_counter_a_pw;



以下为原文

Yes, this is along the lines as to what I'm looking for.  I have the following code that I generated off of the tips.  I have an input signal of J3_IO1 which has a counter a_count_pw and is incremented based off of J3_IO1 upon the clk_50mhz.  To hold the value I save it in a_count_pw_reported.  Am I close to being long the right path?
 
 test_counter_a_pw: process(J3_IO1, a_count_rst, clk_50mhz)
  begin
  if a_count_rst='1' then
       a_count_pw <= X"00000000";
   a_count_pw_reported <= a_count_pw_reported;
  elsif clk_50mhz'event and clk_50mhz='1' then 
  if  J3_IO1'event and J3_IO1='1' then
        a_count_pw <= a_count_pw + 1;
       else
         a_count_pw <= a_count_pw; 
   a_count_pw_reported <= a_count_pw;   
      end if;      
  
    end if;
  end process test_counter_a_pw;

如果您尝试合成此代码，将会遇到很多错误。
尝试用简单的同步方法来思考
countnrs和D触发器。
不要在任何不是“时钟”的事件上使用'event关键字。
所以
如果你想在输入脉冲上看到一个事件，请运行它
2 D触发器并检查是否有那些触发器的输出
比赛。
注意：甚至不要只考虑使用一个触发器
并将其与输入信号进行比较！
生成“事件”
用这种方法不能保证工作，因为
输入与时钟不同步，所以时间
输入改变，直到下一个时钟边沿无法计数
超过任何有用的延迟时间。
这是一个同步过程：
test_counter_a_pw：process（clk_50mhz） - 同步进程仅依赖于时钟edgebeginif clk_50mhz'event和clk_50mhz ='1'然后 - 同步进程，时钟边缘为外“if”如果a_count_rst ='1'那么 - 这现在是
同步复位a_count_pw a_count_pw_reported否则J3_IO1_q J3_IO1_qq如果J3_IO1_qq ='0'且J3_IO1_q ='1'则 - 检测上升沿a_count_pw elsif J3_IO1_qq ='1'且J3_IO1_q ='0'然后 - 检测下降沿a_count_pw_reported否则a_count_pw结束如果结束
if; end process test_counter_a_pw;
-  Gabor
-  Gabor



以下为原文

You're going to get lots of errors if you try to synthesize this code.
Try to think in terms of what you can do with simple synchronous
countnrs and D flip-flops.
 
Don't use the 'event keyword on anything that's not "the" clock.  So
if you want to see an event on the input pulse, run it through
2 D flip-flops and check to see whether the output of those flops
match.  NOTE:  Don't even think of using just one flip-flop
and comparing it to the input signal!  The "event" generated
with this approach is not guaranteed to work because the
input is not synchronous to the clock, so the time when
the input changes until the next clock edge cannot be counted
on to be more than any useful delay time.
 
Here's a synchronous process:
 
test_counter_a_pw: process(clk_50mhz) -- Synchronous process depends ONLY on clock edge
begin
 if clk_50mhz'event and clk_50mhz='1' then -- Synchronous process, clock edge is outer "if"
  if a_count_rst='1' then -- this is now a synchronous reset
   a_count_pw <= X"00000000";
   a_count_pw_reported <= a_count_pw_reported; -- This line is now superfluous, anything not explicitly changed keeps its value in VHDL
  else
   J3_IO1_q <= J3_IO1;  -- First D FF stage (common synchronization point)
   J3_IO1_qq <= J3_IO1_q; -- Second D FF stage for edge detect
   if  J3_IO1_qq = '0' and J3_IO1_q = '1' then -- Detect rising edge
     a_count_pw <= X"00000000"; -- Start from 0 at rising edge
   elsif J3_IO1_qq = '1' and J3_IO1_q = '0' then -- Detect falling edge
     a_count_pw_reported <= a_count_pw;  -- Capture count
   else
     a_count_pw <= a_count_pw + 1;
   end if
  end if;
end process test_counter_a_pw;


-- Gabor

-- Gabor

你应该牢记Gabor在他的帖子中所说的一切。
如果您对Gabor所说的内容有任何疑问或意见，请提及。
Gabor描述的是基本原则，而不仅仅是无聊的细节。
2. Gabor所做的最重要的一点就是J3_IO1输入信号的同步。
您是否了解Gabor对J3_IO1使用的重要性？
3.在进行Gabor更改后，您可能会发现同步重置到a_count_pw计数器没有任何意义。
脉冲前沿检测足以复位计数器。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

1.  You should take to heart everything Gabor said in his post.  If you have any questions or disagreements with what Gabor said, you should mention them.  Gabor is describing fundamental principles, not just frivolous details.
 
2.  The one change Gabor made that should be most important to you is the synchronisation of the J3_IO1 input signal.  Do you understand the importance of Gabor's changes to the use of J3_IO1?
 
3.  After making Gabor's changes, you may find that there is no purpose for the synchronous reset  to the a_count_pw counter.  The pulse leading edge detect is sufficient for reset of the counter.
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

ntropy写道：
是的，这与我正在寻找的是一致的。
我有以下代码，我生成的提示。
我有一个J3_IO1的输入信号，它有一个计数器a_count_pw，并在clk_50mhz时基于J3_IO1递增。
要保存该值，我将其保存在a_count_pw_reported中。
我接近长路的正确道路吗？
test_counter_a_pw：进程（J3_IO1，a_count_rst，clk_50mhz）开始，如果a_count_rst ='1'则a_count_pw a_count_pw_reported elsif clk_50mhz'event和clk_50mhz ='1'然后如果J3_IO1'event和J3_IO1 ='1'则a_count_pw否则a_count_pw a_count_pw_reported结束if;
万一;
结束过程test_counter_a_pw;
几个问题：
a）灵敏度列表中唯一应该是时钟和异步复位。
这是VHDL 101。
b）你需要使用ieee.numeric_std.all;
在源文件的顶部。
c）将a_count_pw声明为自然范围0到CNTMAX;
其中CNTMAX是您期望的最大脉冲宽度计数。
d）通过将计数器信号声明为自然信号，您的复位分配只是a_count_pw
e）正如其他人所指出的那样，'event属性必须仅应用于时钟。
您需要将J3_IO1延迟一个时钟才能找到它的边沿。
你应该同步它。
----------------------------是的，我这样做是为了谋生。



以下为原文

 

ntropy wrote:
Yes, this is along the lines as to what I'm looking for.  I have the following code that I generated off of the tips.  I have an input signal of J3_IO1 which has a counter a_count_pw and is incremented based off of J3_IO1 upon the clk_50mhz.  To hold the value I save it in a_count_pw_reported.  Am I close to being long the right path?
 
 test_counter_a_pw: process(J3_IO1, a_count_rst, clk_50mhz)
  begin
  if a_count_rst='1' then
       a_count_pw <= X"00000000";
   a_count_pw_reported <= a_count_pw_reported;
  elsif clk_50mhz'event and clk_50mhz='1' then 
  if  J3_IO1'event and J3_IO1='1' then
        a_count_pw <= a_count_pw + 1;
       else
         a_count_pw <= a_count_pw; 
   a_count_pw_reported <= a_count_pw;   
      end if;      
  
    end if;
  end process test_counter_a_pw;

 
Several problems:
a) the only thing that should be on the sensitivity list is the clock and the async reset. This is VHDL 101.
b) you need to use ieee.numeric_std.all; at the top of your source file.
c) Declare a_count_pw as a natural range 0 to CNTMAX; where CNTMAX is the largest pulse width count you expect.
d) By declaring the counter signal as a natural, your reset assignment is simply a_count_pw <= 0;
e) As others have noted, the 'event attribute must be applied only to clocks. You need to delay J3_IO1 by one clock to find its edge. And you should synchronize it.
----------------------------Yes, I do this for a living.

非常感谢Gabor。
这很好用。



以下为原文

Thank you so much Gabor.  This works great.

ntropy写道：非常感谢Gabor。
这很好用。
你了解Gabor代码中的想法以及Gabor设计与你的设计之间的区别吗？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

ntropy wrote:
Thank you so much Gabor.  This works great.

Do you understand the ideas in Gabor's code and the differences between Gabor's design and yours ?
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

嗨，我是VHDL的新手。
我正在尝试将这个代码实现到一个程序中，该程序将信号的脉冲宽度显示在basys2板上的七段显示器上，但当我将代码下载到板上时，它只显示“0001”，我发现它只显示1来自
“a_count_pw + 1”的部分。
它看起来只是添加1，即使没有输入信号也是如此。
我也收到此警告“输入永远不会被使用。如果该端口属于顶级块或者属于子块，则该端口将被保留并保持未连接状态，并保留该子块的层次结构。”
这应该是我对信号的输入？
这是我的代码。
非常感谢任何帮助，谢谢。
顶部模块：main_top  -  Behaviral（main_top.vhd）
库IEEE;使用IEEE.STD_LOGIC_1164.ALL;使用IEEE.NUMERIC_STD.ALL;使用IEEE.STD_LOGIC_UNSIGNED.all;实体main_top是端口（J3_IO1：在std_logic中; mclk：在STD_LOGIC中; btn：在STD_LOGIC_VECTOR中（3 downto 0）; a_to_g
：out STD_LOGIC_VECTOR（6 downto 0）; an：out STD_LOGIC_VECTOR（3 downto 0）; dp：out STD_LOGIC）; end main_top; architecture main_top issignal的行为a_count_rst：STD_LOGIC;信号a_count_pw：STD_LOGIC_VECTOR（15 downto 0）;信号a_count_pw_reported：
STD_LOGIC_VECTOR（15 downto 0）;  - 信号J3_IO1：STD_LOGIC;信号J3_IO1_q：STD_LOGIC;信号J3_IO1_qq：STD_LOGIC;组件主端口（x：在STD_LOGIC_VECTOR（15 downto 0）; clk：在STD_LOGIC中; clr：在STD_LOGIC中; a_to_g：
out STD_LOGIC_VECTOR（6 downto 0）; an：out STD_LOGIC_VECTOR（3 downto 0）; dp：out STD_LOGIC）; end component;  -  signal a_count_pw：STD_LOGIC_VECTOR（15 downto 0）; signal x：STD_LOGIC_VECTOR（15 downto 0）; beginprocess
（mclk，J3_IO1） - 同步过程仅取决于时钟edgebeginif mclk'event和mclk ='1'
en  - 同步过程，如果a_count_rst ='1'则时钟边缘为外“if” - 这现在是同步复位a_count_pw a_count_pw_reported否则J3_IO1_q J3_IO1_qq如果J3_IO1_qq ='0'且J3_IO1_q ='1'那么 - 检测上升
edge a_count_pw elsif J3_IO1_qq ='1'和J3_IO1_q ='0'然后 - 检测下降沿a_count_pw_reported else x end if;
结束如果;结束如果;
结束过程;
--x X1：主端口映射（x => x，clk => mclk，clr => btn（3），a_to_g => a_to_g，an => an，dp => dp）;  -  end main_top; end Behaviral
;
这是用于多路复用显示器的下一个模块。
模块：X1  - 主要 - 行为病毒（main.vhd）
库IEEE;使用IEEE.STD_LOGIC_1164.ALL;使用IEEE.STD_LOGIC_UNSIGNED.all;实体main是端口（x：在STD_LOGIC_VECTOR（15 downto 0）; clk：在STD_LOGIC中; clr：在STD_LOGIC中; a_to_g：out STD_LOGIC_VECTOR（6 downto 0
）; an：out STD_LOGIC_VECTOR（3 downto 0）; dp：out STD_LOGIC; btn：在STD_LOGIC_VECTOR（3 downto 0）; J3_IO1：在STD_LOGIC; a_count_pw：在STD_LOGIC_VECTOR（15 downto 0））; end main; architecture Behaviral of main
issignal s：STD_LOGIC_VECTOR（1 downto 0）;信号aen：STD_LOGIC_VECTOR（3 downto 0）;信号clkdiv：STD_LOGIC_VECTOR（20 downto 0）;信号数字：STD_LOGIC_VECTOR（3 downto 0）;开始sd dp --4到1多路复用
进程（s，x）开始情况s是“00”=>数字当“01”=>数字时“10”=>数字当其他=>数字结束情况;
结束过程;
process（digit）begin case digit是当X“1”=> a_to_g时X“1”=> a_to_g当X“2”=> a_to_g时X“3”=> a_to_g当X“4”=> a_to_g时X
“5”=> a_to_g当X“6”=> a_to_g时X“7”=> a_to_g当X“8”=> a_to_g时X“9”=> a_to_g当X“A”=> a_to_g时X“B
“=> a_to_g当X”C“=> a_to_g时X”D“=> a_to_g当X”E“=> a_to_g时其他=> a_to_g结束情况;
结束过程;
--digit控制进程（s，aen）开始if aen（conv_integer（s））='1'然后an（conv_integer（s））结束if;
结束过程;
- 如果clr ='1'然后clkdiv'0'），则开始分频器进程（clk，clr）;
elsif clk'event和clk ='1'然后clkdiv结束if;
结束过程;结束行为;



以下为原文

Hi I am new to VHDL. I am trying to implement this code into a program that displays the pulse width of a signal onto the seven segment display on the basys2 board but when I download the code onto the board it just displays "0001" I figured out its just showing 1 from the part that does "a_count_pw+1". it looks like it just adds 1 and that it even when there is no input signal. I also get this warning "Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved." this is supposed to be my input for the signal? Here is my code. Any help is greatly appreciated thank you.
 
Top module: main_top - Behaviral(main_top.vhd)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity main_top is
    port(
            J3_IO1 : in std_logic;
            mclk : in STD_LOGIC;
            btn : in STD_LOGIC_VECTOR(3 downto 0);
            a_to_g : out STD_LOGIC_VECTOR(6 downto 0);
            an : out STD_LOGIC_VECTOR(3 downto 0);
            dp : out STD_LOGIC
         );
end main_top;

architecture Behaviral of main_top is
signal a_count_rst: STD_LOGIC;
signal a_count_pw: STD_LOGIC_VECTOR(15 downto 0);
signal a_count_pw_reported: STD_LOGIC_VECTOR(15 downto 0);
--signal J3_IO1 : STD_LOGIC;
signal J3_IO1_q : STD_LOGIC;
signal J3_IO1_qq : STD_LOGIC;

component main
    port(
        x : in STD_LOGIC_VECTOR(15 downto 0);
        clk : in STD_LOGIC;
        clr : in STD_LOGIC;
        a_to_g : out STD_LOGIC_VECTOR (6 downto 0);
        an : out STD_LOGIC_VECTOR (3 downto 0);
        dp : out STD_LOGIC 
    );
end component;

--signal a_count_pw: STD_LOGIC_VECTOR(15 downto 0);
signal x: STD_LOGIC_VECTOR (15 downto 0);
begin

process(mclk, J3_IO1)-- Synchronous process depends ONLY on clock edge
begin
 if mclk'event and mclk='1' then -- Synchronous process, clock edge is outer "if"
  if a_count_rst='1' then -- this is now a synchronous reset
   a_count_pw <= b"0000000000000000";
   a_count_pw_reported <= a_count_pw_reported; -- This line is now superfluous, anything not explicitly changed keeps its value in VHDL
  else
   J3_IO1_q <= J3_IO1;  -- First D FF stage (common synchronization point)
   J3_IO1_qq <= J3_IO1_q; -- Second D FF stage for edge detect
   if  J3_IO1_qq = '0' and J3_IO1_q = '1' then -- Detect rising edge
     a_count_pw <= b"0000000000000000"; -- Start from 0 at rising edge
   elsif J3_IO1_qq = '1' and J3_IO1_q = '0' then -- Detect falling edge
     a_count_pw_reported <= a_count_pw;  -- Capture count
   else
     x <= a_count_pw + 1;
   end if;
  end if;
 end if;
end process;
   
    --x <= a_count_pw;
    X1 : main port map
            (x=>x, clk=>mclk, clr=>btn(3), a_to_g=>a_to_g, an=>an, dp=>dp);

--end main_top;

end Behaviral;
 
 
This is the next module for multiplexing the display.
 
Module: X1 - main - Behaviral (main.vhd)
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity main is
    port(
        x : in STD_LOGIC_VECTOR(15 downto 0);
        clk : in STD_LOGIC;
        clr : in STD_LOGIC;
        a_to_g : out STD_LOGIC_VECTOR (6 downto 0);
        an : out STD_LOGIC_VECTOR (3 downto 0);
        dp : out STD_LOGIC;
        btn : in STD_LOGIC_VECTOR(3 downto 0);
        J3_IO1 : in STD_LOGIC;
        a_count_pw : in STD_LOGIC_VECTOR(15 downto 0)
    );
end main;

architecture Behaviral of main is
signal s : STD_LOGIC_VECTOR (1 downto 0);
signal aen : STD_LOGIC_VECTOR (3 downto 0);
signal clkdiv : STD_LOGIC_VECTOR (20 downto 0);
signal digit : STD_LOGIC_VECTOR (3 downto 0);



begin
    s <= clkdiv(18 downto 17);
    aen <= "1111";
    dp <= '1';
    
    
    --4 to 1 multiplex
    process(s, x)
    begin
        case s is
        when "00" => digit <= x(3 downto 0);
        when "01" => digit <= x(7 downto 4);
        when "10" => digit <= x(11 downto 8);
        when others => digit <= x(15 downto 12);
        end case;
    end process;
    
    
    process(digit)
    begin
        case digit is
            when X"0" => a_to_g <= "1000000"; --0
            when X"1" => a_to_g <= "1111001"; --1
            when X"2" => a_to_g <= "0100100"; --2
            when X"3" => a_to_g <= "0110000"; --3
            when X"4" => a_to_g <= "0011001"; --4
            when X"5" => a_to_g <= "0010010"; --5
            when X"6" => a_to_g <= "0000010"; --6
            when X"7" => a_to_g <= "1011000"; --7
            when X"8" => a_to_g <= "0000000"; --8
            when X"9" => a_to_g <= "0010000"; --9
            when X"A" => a_to_g <= "0001000"; --A
            when X"B" => a_to_g <= "0000011"; --b
            when X"C" => a_to_g <= "1000110"; --C
            when X"D" => a_to_g <= "0100001"; --d
            when X"E" => a_to_g <= "0000110"; --E
            when others => a_to_g <= "0001110"; --F
        end case;
    end process;
    
    --digit control
    process(s, aen)
    begin
        an <= "1111";
        if aen(conv_integer(s)) = '1' then
            an(conv_integer(s)) <= '0';
        end if;
    end process;
    
    --clock divider
    process(clk, clr)
    begin
        if clr ='1' then
            clkdiv <= (others => '0');
        elsif clk'event and clk = '1' then
            clkdiv <= clkdiv +1;
        end if;
    end process;

end Behaviral;
 
 

看起来对我来说是一个非常简单的错误：a_count_pw永远不会增加。
它只被设置为零，这意味着大多数其他代码什么都不做。



以下为原文

Looks like a very simple mistake to me: a_count_pw is never incremented. It's only ever set to zero, which means that most of the other code does nothing.