如何测量脉冲宽度

只要pulse ='1'，就保持在“High”状态，当pulse ='0'时，转换为“Low”？



以下为原文

Stay in "High" as long as pulse='1', and do the transition to "Low" when pulse='0' ?

如果脉冲从高到低，它应该保持计数直到下一个上升沿为高，这是行不通的。
例如，脉冲可能是这样的 
第一个上升沿第二个上升沿 
-------------- ----------------------
------ --------------------------------
宽度在第一和第二之间。



以下为原文

That would not work becuase  if the pulse from high then low it should stay counting until the next rising edge is high.
 
for instance the pulse may be something like this
     first rising edge                                      second rising edge
        --------------                                            ----------------------
------                   --------------------------------
 
The width is between the first and second.

reg [1：0] insync;
//同步异步脉冲输入
reg [15：0] pw_ctr，pw_save;
//脉冲宽度计数器，加上快照复制
总是@（posedge clock） 
insync：脉冲输入为'0' 
开始 
pw_save：脉冲输入高吗？ 
pw_ctr：脉冲输入为'1' 
pw_ctr
从技术上讲，有三种状态：
1.输入低，保持低位
2.输入低，但即将走高
3.输入很高
你需要3个州
清除柜台
允许计数器递增
当计数器既不清除也不计数时保存计数器值
如果您不需要在快照寄存器中保存计数器的副本，则只需要2个状态。
编码此问题的方法有很多种。
这只是一个例子。
- 鲍勃埃尔金德
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以下为原文

 
reg [1:0]  insync;            // synchronise async pulse inputreg [15:0] pw_ctr, pw_save;   // pulse width counter, plus snapshot copyalways @(posedge clock)  insync  <=  {insync[0], pulse_input};  // sync the async pulse inputalways @(posedge clock)   case (insync[1])     1'b0:                       // state #1 and #2: pulse input is '0'       begin         pw_save  <=  pw_ctr;    // save the last pulse width count         if (insync[0] == 1)     // state #2: is pulse input going high?            pw_ctr <= 16'h0000;  // yes, clear the pulse width counter       end     1'b1:                       // state #3: pulse input is '1'         pw_ctr <= pw_ctr + 1;   // count while pulse input is '1'   endcaseTechnically, there are three states:

1.  Input is low, and staying low
2.  Input is low, but about to go high
3.  Input is high

You need 3 states to

• clear the counter
  
• allow the counter to increment
  
• save the counter value when counter is neither clearing or counting
  

If you don't need to save a copy of the counter in a snapshot register, then you only need 2 states.
 
There are many many ways of coding this problem.  This is just one example.
 
-- Bob Elkind
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假设我根据你的解释只有两个状态，当我不需要拍摄快照然后???
将是pulse ='1'/ c ++并且pulse ='0'/ c = 0
您的代码也是什么语言？



以下为原文

suppose i just have two states according to your explaination when i don't need to take the snapshot then the ??? will be pulse='1'/c++ and pulse='0'/c=0
 
Also what language is your code in?

假设我根据你的解释只有两种状态
当我不需要拍摄快照然后???
将会
pulse ='1'/ c ++和pulse ='0'/ c = 0
同意，在你描述的例子中只需要两个状态，就像你描述它们一样。
您的代码也是什么语言？
Verilog的。
- 鲍勃埃尔金德
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以下为原文

suppose i just have two states according to your explaination when i don't need to take the snapshot then the ??? will be pulse='1'/c++ and pulse='0'/c=0

Agreed, only two states needed in the example you describe, exactly as you describe them.

Also what language is your code in?

Verilog.
 
-- Bob Elkind
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假设我根据你的解释只有两种状态
当我不需要拍摄快照然后???
将会
pulse ='1'/ c ++和pulse ='0'/ c = 0
同意，在你描述的例子中只需要两个状态，就像你描述它们一样。
您的代码也是什么语言？
Verilog的。
- 鲍勃埃尔金德



以下为原文

suppose i just have two states according to your explaination when i don't need to take the snapshot then the ??? will be pulse='1'/c++ and pulse='0'/c=0

Agreed, only two states needed in the example you describe, exactly as you describe them.

Also what language is your code in?

Verilog.
 
-- Bob Elkind

我仍然无法理解它是如何工作的，因为我找到脉冲的宽度，如果脉冲变低，它应该仍然测量它的值，直到脉冲为高时的下一个上升沿。
就像我之前画的那样 
第一个上升边缘第二
上升的边缘 
-------------- 
----------------------
------ --------------------------------



以下为原文

I am still unable to understand how that would work, because i am finding the width of the pulse, if the pulse went low it should still measure the value of that until the next rising edge when pulse is high. Like what i drew before
 
    first rising edge                                      second rising edge
        --------------                                            ----------------------
------                   --------------------------------                
        <------------------------Pulse Width-------------->     
 

a707写道：
如果脉冲从高到低，它应该保持计数直到下一个上升沿为高，这是行不通的。
...
啊 - 所以你不是在测量脉冲宽度，而是测量信号的周期......
而且，Bob之前发布的代码几乎可以满足您的需求 - 修改它时应该很简单，以便在输入信号较低时进行计数...



以下为原文

 

a707 wrote:
That would not work becuase  if the pulse from high then low it should stay counting until the next rising edge is high.
...

 
Ah - so you are not measuring the pulse width, but rather the period of the signal...
 
And also, the code posted by Bob previously does almost what you want - it should be simple to modify it to also count when the input signal is low...

任何人都可以将该代码转换为Verilog吗？
因为我通常在VHDL工作



以下为原文

Can anyone convert that code to Verilog? becuase i normally work in VHDL

因此，如果我测量信号的周期，那么状态图会不同吗？
您的逻辑变得更简单，您只有一个事件需要检测
reg [1：0] insync;
//同步异步脉冲输入
reg [15：0] pw_ctr，pw_save;
//脉冲宽度计数器，加上快照复制
总是@（posedge clock） 
insync：检测输入上升沿，开始新的脉冲周期 
开始 
pw_save：不是状态＃1 
pw_ctr
从技术上讲，有两种状态：
1.投入很低，即将走高
2.输入不低或不高
你需要2个州
保存计数器值并清除计数器
允许计数器递增
- 鲍勃埃尔金德
上升的输入边缘
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以下为原文

So if i was measuring the period of the signal, would the state diagram be different?

Your logic becomes simpler, you have only one event to detect
 
reg [1:0]  insync;            // synchronise async pulse inputreg [15:0] pw_ctr, pw_save;   // pulse width counter, plus snapshot copyalways @(posedge clock)  insync  <=  {insync[0], pulse_input};  // sync the async pulse inputalways @(posedge clock)  if (insync == 2'b01)       // state #1: detect input rising edge, beginning a new pulse cycle    begin      pw_save  <= pw_ctr     // save snapshot of the current cycle period
      pw_ctr   <= 16'h0000;  // init counter to '0' or to '1', your choice    end  else                       // state #2: not state #1      pw_ctr <= pw_ctr + 1;  // count until next cycle beginsTechnically, there are two states:

1.  Input is low and about to go high
2.  Input is not low or not about to go high

You need 2 states to

• save the counter value and clear the counter
  
• allow the counter to increment
  

-- Bob Elkind
rising edge of inputSIGNATURE:
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所以这是不正确的？脉冲



以下为原文

so this would be incorrect?

pulse <= pulse + '1' / c++ and pulse <= pulse + '0' / value<=c

所以这是不正确的？脉冲
如果你没有清楚地理解你正在使用的语法（或语言），我会毫不犹豫地回答。你会翻译成普通的英语文本，还是指向你使用的语言的参考手册？ -  Bob Elkind
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以下为原文

so this would be incorrect?
pulse <= pulse + '1' / c++ and pulse + '0''  / value<=c

I hesitate to answer without a clear understanding of the syntax (or language) you are using.
Would you translate to plain English language text, or point me to a reference manual for the language you are using?

-- Bob Elkind
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谢谢你的翻译。
首先是在州1
- 当脉冲为0时，计数保持为0（脉冲='0'/ c = 0）
- 当脉冲为1时，计数开始递增（pulse ='1'/ c ++）
你描述了两种状态，对吗？
状态1：[脉冲为'0']和状态2：[脉冲为'1']。
其次在州2这是我坚持的地方
- 它应首先进行计数，直到它看到下一个上升沿（?????? / c ++）
- 当检测到上升沿时，它应该返回到状态1，
因此计数值将被保存。
（pulse = done / value
如果状态1为（脉冲='0'），状态如何在检测到上升沿时返回状态1？
我想你正在描述两种不同的状态，一种检测上升沿，另一种检测下降沿
我想你（或者也许是我）很困惑。
这是一个备用状态图。
这有意义吗？
+  - >状态1 -------------->状态2 ------------>状态3 ------------
--- +
|
脉冲为'0'脉冲为'1'脉冲为'1'|
|
无脉冲计数（单周期）增量脉冲计数|
|
保存计数值init计数值||
|
+ -------------------------------------------------
------------------------------ +
我做对了吗？
这有意义吗？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

Thank you for the translation.

Firstly in State 1
- when pulse is 0 then count remain at 0    (pulse = '0' / c=0)
- when pulse is 1 then count start incrementing (pulse = '1' / c++)

You have described two states, correct?  State 1: [pulse is '0'] and State 2: [pulse is '1'].

Secondly in State 2  This is where i am stuck on
- it should first contuine counting until it sees the next rising edge ( ??????/ c++)
- it should return back to State 1 when a rising edge is detected, hence the count value will be saved. (pulse = done / value <= c)

How can a state return to State 1 on a detection of a rising edge, if State 1 is for (pulse = '0') ?
I think you are describing two different states, one which detects a rising edge and one which detects a falling edge
 
I think you (or maybe it's me) are confused.  Here is an alternate state diagram.  Does this make sense?

+-->  State 1  -------------->  State 2   ------------>  State 3 ---------------+
|     pulse is '0'              pulse is '1'             pulse is '1'           |

|     no pulse counting         (single cycle)           increment pulse count  |

|     save count value          init count value                                |
|                                                                               |
+-------------------------------------------------------------------------------+

Did I get this right?  Does this make sense?
 
-- Bob Elkind
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不，我认为你的第一个解决方案有2个状态是正确的。我是那个被混淆的人，因此它让你很困惑。



以下为原文

no i think your first solution with 2 states were correct.
I'm the one that was confused hence it confused you.