如何使用verilog为FPGA制作通用字节写

对于像256 x 12这样的小型存储器没有意义，但第三种选择是在1位宽模式下使用RAMB，因此每位需要一个RAMB，总共12个。
根据设备的不同，这将创建至少8K或16K深存储器。
至于推断这种RAM，您可能需要进行试验，以确保综合工具能够将您的代码理解为RAM模板。
当然应该创建一个通用的1位宽RAM作为模块，然后将其中的12个实例化为一个实例化数组（或生成for循环）。
目前尚不清楚这些工具是否可以通过简单编写每位写入启用来满足您的需求，但值得一试。
这可以在程序循环中编码，如：
整数i;
总是@（posedge wr_clk）

for（i = 0; i 以下为原文

It wouldn't make sense for a small memory like 256 x 12, but a third option is to use the RAMB in 1 bit wide mode, so you would need one RAMB per bit, 12 in all. Depending on the device, this would create a minimum of 8K or 16K deep memory.

As far as inferring this sort of RAM, you may need to experiment in order to make sure that the synthesis tool can understand your code to be a RAM template. It certainly should work to create a generic 1-bit wide RAM as a module and then instantiate 12 of them as an array of intantiations (or in a generate for loop). It's not clear whether the tools would give you what you want by simply coding a per-bit write enable, but it's worth a try. That could be coded in a procedural loop like:

integer i;

always @ (posedge wr_clk)
for (i = 0;i < WIDTH;i = i + 1) if (wr_ena) RAM[wr_addr] <= din;

If you're lucky the tools will fit that into distributed RAM for you.

-- Gabor

问答对人有帮助，内容完整，我也想知道答案 0 喜我知道如何使用verilog为FPGA制作通用字节写，字写存储器模型。但有没有办法制作一点写内存模型？我在网上看了很多但找不到一个。而我所做的存储器模型最终会在读写时产生几个延迟周期（因为位写特性）。因此，如果某人使用了bitwrite内存模型或知道在哪里找到它们的通用代码（在线链接），那就太好了。感谢advacne的帮助。 ž。以上来自于谷歌翻译以下为原文 hi, i know how to make generic byte write, word write memory models in verilog for FPGAs. but is there any way of making a bit write memory model? i have looked online quite a lot but couldn't find one. and the memory model i am making ends up having a couple of cycles of delay in reads and write (because of the bit-write nature). so if someone has worked with bitwrite memory models or knows where to find generic code for them (online link), that would be great. thanks in advacne for the help. z. 0
2019-4-16 10:48:55　　评论淘帖0 邀请回答您可以邀请以下用户，快速回答问题 × asd008 该类别下有 32 个回答。邀请回答 aaaa321 该类别下有 27 个回答。邀请回答 doublelove 该类别下有 26 个回答。邀请回答 vynywrwr 该类别下有 21 个回答。邀请回答 hgjhgd 该类别下有 19 个回答。邀请回答 bwerwer 该类别下有 18 个回答。邀请回答 hanyan533 该类别下有 18 个回答。邀请回答 Jaionm 该类别下有 18 个回答。邀请回答 handsomelchcpp 该类别下有 17 个回答。邀请回答 wang2222222 该类别下有 17 个回答。邀请回答 ningee 该类别下有 16 个回答。邀请回答 binro 该类别下有 16 个回答。邀请回答 wznnzw 该类别下有 15 个回答。邀请回答 myf888 该类别下有 15 个回答。邀请回答 yhxc 该类别下有 14 个回答。邀请回答 armortech 该类别下有 14 个回答。邀请回答 60user25 该类别下有 14 个回答。邀请回答 zcy615 该类别下有 14 个回答。邀请回答 wanglinhua2627 该类别下有 14 个回答。邀请回答 guotong1984 该类别下有 14 个回答。邀请回答举报李昕萌相关推荐 • 请问AzureRTOS ThreadX/NetXDuo在通用字节池上缓存怎么样 762 • 为减少数据和时钟偏差应遵循哪些通用FPGA编码规则？ 945 • 求一个verilog写的RS232收发3个字节的代码啊！ 3810 • 以FPGA为平台怎么测量脉冲宽度的verilog语言 6512 • 基于FPGA，如何用Verilog实现12864上的时间曲线图？？ 3493 • 怎么将FPGA的IO设置为JTAG模式的verilog代码？ 2484 • 24c256写满一页后怎么进行翻页操作？ 1817 • 用于16位gpif 2设计的FPGA主verilog代码 2798 • 6678 srio写操作时字节对齐问题 3041 • modbus协议为什么发送时是用两个字节表示的寄存器数量，返回时却是一个字节的字节数？ 19589 2个回答

答案对人有帮助，有参考价值 0 问题（可能）不是与Verilog有关，而是与FPGA中的Block RAM的能力有关。 RAMB36（和其他RAM）每字节启用（仅限）; 每个启用控制写入RAM的8（或9）位。块RAM没有更小的粒度。如果您真的需要位写入功能，您有两种选择： - 使用分布式RAM - 每个RAM为64x1位，因此本身是可写入的，但RAM很小; 建造大型资源将需要大量资源，并且随着深度开始变大而开始变慢 - 在Block RAM外部实现读 - 修改 - 写 - 每次写入RAM首先读取整个字节/字，修改要更改的位，然后将整个字节/字写回RAM - 当然，这需要至少2个（如果不是3个）时钟周期来执行操作，并且要么不需要每个时钟都进行操作，要么使用双端口RAM Avrum 以上来自于谷歌翻译以下为原文 The issue is (probably) not with the Verilog but with the capability of the block RAMs in the FPGA. The RAMB36 (and other RAMs) have enables per byte (only); each enable controls the writing of 8 (or 9) bits of the RAM. There is no smaller granularity for the block RAM. If you really need bit write capability, you have two choices: - use distributed RAM - each RAM is 64x1 bit, so is inherently bit writeable, but the RAMs are small; building large ones will take a lot of resources and will start getting slow as the depth starts getting larger - implement a read-modify-write outside the block RAM - each write to the RAM first reads the entire byte/word, modifies the bits you want to change, and writes back the entire byte/word to the RAM - of course, this requires at least 2, if not 3 clock cycles to do an operation, and either requires that operations not be done every clock, or that you use a dual ported RAM Avrum

2019-4-16 10:58:06 评论举报陈玉筠

答案对人有帮助，有参考价值 0 对于像256 x 12这样的小型存储器没有意义，但第三种选择是在1位宽模式下使用RAMB，因此每位需要一个RAMB，总共12个。根据设备的不同，这将创建至少8K或16K深存储器。至于推断这种RAM，您可能需要进行试验，以确保综合工具能够将您的代码理解为RAM模板。当然应该创建一个通用的1位宽RAM作为模块，然后将其中的12个实例化为一个实例化数组（或生成for循环）。目前尚不清楚这些工具是否可以通过简单编写每位写入启用来满足您的需求，但值得一试。这可以在程序循环中编码，如：整数i; 总是@（posedge wr_clk） for（i = 0; i 以下为原文 It wouldn't make sense for a small memory like 256 x 12, but a third option is to use the RAMB in 1 bit wide mode, so you would need one RAMB per bit, 12 in all. Depending on the device, this would create a minimum of 8K or 16K deep memory. As far as inferring this sort of RAM, you may need to experiment in order to make sure that the synthesis tool can understand your code to be a RAM template. It certainly should work to create a generic 1-bit wide RAM as a module and then instantiate 12 of them as an array of intantiations (or in a generate for loop). It's not clear whether the tools would give you what you want by simply coding a per-bit write enable, but it's worth a try. That could be coded in a procedural loop like: integer i; always @ (posedge wr_clk) for (i = 0;i < WIDTH;i = i + 1) if (wr_ena) RAM[wr_addr] <= din; If you're lucky the tools will fit that into distributed RAM for you. -- Gabor

2019-4-16 11:05:57 评论举报杨玲

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