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我设置一些I2C通信(虽然,快速阅读的UART和SPI组件、数据表我认为类似的问题可能存在过),我通过API的困惑。
似乎所有的发送/接收功能被阻断。有没有启动传输功能,让硬件跟它在速度较慢的I2C时钟,然后让它触发一个中断? 我可能会感到困惑。我认为硬件I2C收发器的想法是让它运行在时钟的缓慢而处理器做别的事情上快速的时钟?或是这种情况下通过在直接与寄存器的支持,但不支持通过API吗? 以上来自于百度翻译 以下为原文 I'm setting up some I2C communications (although, quickly perusing the datasheet for the UART and SPI components, I think that analogous issues may exist there too) and I'm confused by the API. It seems that all the sending/receiving functions are blocking. Are there no functions for initiating a transfer, letting the hardware mess with it at the much slower I2C clock, and then have it trigger an interrupt? I may just be confused. I thought the idea of the hardware I2C transceiver was to allow it to operate on the slow clock while the processor does other things on the fast clock? Or is this scenario supported through messing directly with the registers, but not supported through the API? |
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并非所有API都阻止API。当CPU忙于其他事情时,有可能将I2C数据传输任务委托给I2C硬件块。这两种非阻塞语句是可能的,
I2C.MistRealWrdBuf(UIT8 SLaveLoad,UTI8*WRDATA,UTI8CNT,UIT8模式)UTI8I2CYMASTEMADRADBF(UIT8 SLaveLoad,UTI8*RDDATA,UTIN CNT,UIT8模式),PalaMigor模式决定了传输的性质(完整的I2C传输,无停止位,从重复启动开始等)。 注意,在数据表中有其他API集被清楚地描述为阻塞语句: 例子:UTI8I2C.MasksEngESTEnter(UTI8 SLaveAdvices,UIT8 8RNW) uTI8I2C.MigWrimeWrimeEnter字节(UIT8字节) 以上来自于百度翻译 以下为原文 Not all APIs are blocking APIs. It is possible to delegate the I2C data transfer job to the I2C hardware block while the CPU is busy with something else. This is possible with the two non-blocking statements,
Note that there are other set of APIs which are clearly described as blocking statement in the datasheet: Example: uint8 I2C_MasterSendStart(uint8 slaveAddress, uint8 R_nW) uint8 I2C_MasterWriteByte(uint8 theByte) |
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啊,他们也是。
我认为这样的代码基本上可以吗? //这个函数应该传输一个字节(奴隶的登记地址)的奴隶,然后发出重启,然后从奴隶的两个字节 readslaveregister UInt16(uint8 slaveaddress,uint8 slaveregisteraddress) { UIT16结果; UIT8状态; 状态= i2c_masterwritebuf(slaveaddress,&;slaveregisteraddress,sizeof(卡片),i2c_mode_no_stop); //错误处理 / /呼叫FreeRTOS睡眠线程一会儿直到I2C做其事,大概是通过添加一行到其ISR结束,会给我们的信号一旦传递结束或中断 状态= i2c_masterreadbuf(slaveaddress,&;结果,sizeof(uint16),i2c_mode_repeat_start | i2c_mode_complete_xfer); //错误处理 叫FreeRTOS再睡一觉 返回结果; } 以上来自于百度翻译 以下为原文 Ahh, so they are. So am I correct in thinking that code like this will be basically ok? // this function should transfer one byte (the slave's register address) to the slave, then issue a restart, then read two bytes from the slave uint16 ReadSlaveRegister(uint8 slaveAddress, uint8 slaveRegisterAddress) { uint16 result; uint8 status; status = I2C_MasterWriteBuf(slaveAddress, &slaveRegisterAddress, sizeof(uint8), I2C_MODE_NO_STOP); // error handling // call FreeRTOS to sleep this thread for a while until the I2C is done doing its thing, presumably by adding a line to the end of its ISR that will give our semaphore once the transfer is over or breaks status = I2C_MasterReadBuf(slaveAddress, &result, sizeof(uint16), I2C_MODE_REPEAT_START | I2C_MODE_COMPLETE_XFER); // error handling // call FreeRTOS to sleep again in the same way return result; } |
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哦,那它会把读取的第二字节取下来,然后发送一个停止条件吗?(由于指定了I2CyMeDeExoReTyxFER)。
以上来自于百度翻译 以下为原文 Oh, and that it will NAK the 2nd byte of the read and then send a stop condition as well? (Since I2C_MODE_COMPLETE_XFER was specified.) |
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它似乎是这样工作的(直到我不高兴的时候,我有点打嗝,因为我没有事先知道PSOC5是一个小字节)。
有没有比修整自动生成的ISR更好的选择?它似乎不包含自动生成器不会重写的块,它似乎没有回调。 也许组件应该包括一个IrQ输出的选项,当传输完成(成功或其他)时,它会被脉冲,并且我可以把自己的ISR绑定到那个? 以上来自于百度翻译 以下为原文 It does seem to work that way (up to endian-ness, which I had a little hiccup with since I hadn't had prior occasion to learn that the PSoC5 is little-endian). Is there a better option than tinkering with the auto-generated ISR? It doesn't seem to include a block that the auto-generator won't overwrite, it doesn't seem to have a callback. Maybe the component should include an option for an irq output that is pulsed when a transfer completes (successfully or otherwise), and I could hook my own ISR to that? |
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嗨,Doug McClean,
在上一篇文章中,您使用了如下API: 状态= i2c_masterreadbuf(slaveaddress,&;结果,sizeof(uint16),i2c_mode_repeat_start | i2c_mode_complete_xfer); 宏定义 1)I2CI MODEE重复启动= 0x01 2)I2CYMODEXEXCELTEXXFER=0x00 3)I2CyMODENoNOYSTOR= 0x02。 因此,它是确定是否停止产生和repeatstart发布二最低有效位。 当LSB被设置(1)时,重复启动被发送,否则星形传输。 当最后一个LSB被设置(1)时,不生成停止。否则,停止生成。 因此,口语与i2c_mode_complete_xfer是不是真的有必要为它相当于ORing和0x00。 以上来自于百度翻译 以下为原文 Hi Doug McClean, In your previous post, you had used the API as follows: status = I2C_MasterReadBuf(slaveAddress, &result, sizeof(uint16), I2C_MODE_REPEAT_START | I2C_MODE_COMPLETE_XFER); The macro definition for 1) I2C_MODE_REPEAT_START = 0x01 2) I2C_MODE_COMPLETE_XFER = 0x00 3) I2C_MODE_NO_STOP = 0x02. Hence, it is the 2 least significant bits which determine whether STOP is generated and REPEAT START is issued. When LSB is set (1), REPEAT START is sent, else START is sent. When last but one LSB is set (1), STOP is not generated. Else, STOP is generated. Hence, ORing with I2C_MODE_COMPLETE_XFER is not really necessary as it is equivalent to ORing with 0x00. |
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谢谢DASQ,这很有道理。
你有什么建议的建议,以获得中断在硬件的结束和CyPress产生的固件-处理部分的I2C交易? 组件上一个可选的IRQ输出引脚可能需要很多,并且将不必要地连接另一个处理器中断。 也许一个更好的方法是添加另一个与此类似的部分(IXIN由代码生成器保持未修改): 在这里准备阅读缓冲器的地方代码*//********************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************** 到i2cim.c? 不幸的是,在ISR中没有一条线可以添加。如果我理解正确,它需要每个I2CI状态被分配的新的值I2CsSmithIDLE?也许引入一个新的本地名为I2CYSTATEYNEXT,分配I2CySmithIDLE to,然后在嵌套的I/EL逻辑之后有一个位置,但是在将I2CYSTATEY分配给I2CI状态之前,开发者可以向ISR添加一些自定义逻辑。 我要做的是调用FieleStOffice XMeSaleReLogFuffr每当I2C事务的硬件和生成的固件部分完成时,请求它的线程将被调度器唤醒。 以上来自于百度翻译 以下为原文 Thanks dasq, that makes perfect sense. Do you have any advice on the recommended way to get an interrupt at the end of the hardware- and cypress-generated-firmware- handled portion of an I2C transaction? An optional irq output pin on the component might be a lot to ask, and would needlessly tie up another processor interrupt. Perhaps a better approach would be just to add another section similar to this one (which I assume is maintained unmodified by the code generator): /*******************************************/ /* Place code to prepare read buffer here */ /*******************************************/ /* `#START SW_PREPARE_READ_BUF` */ /* `#END` */ to I2C_INT.c? Unfortunately it looks like there is no one line in the ISR where this could be added. If I understand properly, it would need to be each place where I2C_State is assigned the new value I2C_SM_IDLE? Maybe introduce a new local called I2C_State_Next, assign I2C_SM_IDLE to it, and then have one place after all the nested if/else logic but before assigning I2C_State_Next to I2C_State where the developer could add some custom logic to the ISR? What I am trying to do is call the FreeRTOS function xSemaphoreGiveFromISR whenever the hardware-and-generated-firmware part of an I2C transaction is finished, so that the thread that requested it will be awoken by the scheduler. |
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我碰到这回到了论坛,因为我已经尝试了一切我想我还是找不到合适的地方放xsemaphoregivefromisr。
有人有什么建议吗? 以上来自于百度翻译 以下为原文 I'm bumping this back up the forum because I have tried everything I can think of and I still can't find the appropriate place to put the xSemaphoreGiveFromISR. Does anyone have any suggestions? |
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这看起来像一个复杂的问题:
在I2C通信的中断例程内设置空闲状态(当然)。在一个中断例程中引发另一个中断,其中任务切换的RTOS功能被称为有点危险。 所以我们试着烘焙小面包。 如果使用中断驱动轮询,会怎么样?一个定时器中断和检查I2C的状态,当IO完成时释放信号量?由于I2C的冗长I/O(与CPU相比),如果信号量释放比传输结束晚1到10ms,那就无关紧要了。 嗯,我知道事情并不像我刚才写的那么简单,中断例程必须知道开始的I/O和其他事情,但它可以是一种方法。 快乐编码,不要让你被打断 鲍勃 以上来自于百度翻译 以下为原文 That looks like a complicatetd one: The IDLE-State is set (of course) within the interrupt-routine of the I2C communication. To raise another interrupt within an interrupt-routine where a RTOS-function for task-switching is called looks a bit hazardous. So let's try to bake smaller breads. What, if you use an interrupt-driven polling? Ie. a timer that interrupts and just checks for the state of I2C and when it's IO is done releases the Semaphore? Due to the lengthy i/o of I2C (compared to the CPU) it won't matter much, if the semaphore release comes 1 to 10ms later than the end of transmission really was. Well, I know that tis thing is not as easy as I just wrote, the interrupt-routine will have to know about started I/O and other things, but it can be an approach. Happy coding, don't let you be interrupted Bob |
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