2个BUFR输出之间的相位关系是什么

如果处理得当，两个BUFR的输出是同相的。
但是你必须实现电路来同步BUFR计数器，这在UG472（v1.11.2，p.108）“BUFR Alignment”中有概述。
您需要在BUFMR上对输入时钟进行门控，重置两个BUFR，释放BUFR的复位，然后在BUFMR重新启用时钟 - 这可确保两个BUFR分频器同步，因此将具有相同的相位
（4个输入时钟边沿中的哪一个代表BUFR输出的上升沿）......
但...
管理这将很困难。
这些工具不会/不能将逻辑从一个BUFR移动到另一个BUFR。
就布局而言，这两个BUFR输出是独立的时钟。
无论你使用第一个时钟，你需要保留在BUFR的时钟区域，无论你使用第二个时钟区域，你的时钟都将在第二个时钟区域。
没有逻辑可以从一个区域移动到另一个区域。
因此，您的ISERDES将位于一个时钟区域。
如果所有结构逻辑都由另一个BUFR计时，那么ISERDES的输出将有很长的路由到达另一个时钟区域（可能会失败时序）。
为了避免这种情况，您必须确保在BUFR上有足够的流水线级，为ISERDES提供时钟，以确保数据可以直接移动到时钟区域的边界，由另一个时钟拾取
域。
如果处理接收时钟上的数据的逻辑很大（因此需要多个时钟区域），则必须在两个域中的每一个上手动将块分区为逻辑，这通过选择哪个时钟来完成
计时设计的每个部分。
这将非常不方便......
但是，如果你必须这样做，它是可行的 - 它只是非常耗时......
Avrum
在原帖中查看解决方案



以下为原文

If handled properly, the outputs of the two BUFRs are in phase. But you have to implement the circuit to synchronize the BUFR counters, which is outlined in UG472 (v1.11.2, p. 108) "BUFR Alignment". You need to gate the incoming clock at the BUFMR, reset the two BUFRs, release the reset of the BUFRs and then re-enable the clock at the BUFMR - this ensures that the two BUFR dividers are synchronized, and hence will have the same phase (which of the 4 input clock edges represents the rising edge of the BUFR output)...
 
BUT...
 
Managing this is going to be difficult. The tools will not/can not move logic from one BUFR to the other. As far as placer is concerned, these two BUFR outputs are separate clocks. Whatever you clock with the first one will need to remain in that BUFR's clock region, and whatever you clock with the 2nd one will be in the 2nd one's clock region. No logic will be able to be moved from one region to the other.
 
So, your ISERDESs will be in one clock region. If all the fabric logic is clocked by the other BUFR, then there will be long routes from the outputs of the ISERDES to reach the other clock region (which may fail timing). To avoid this, you are going to have to make sure that you have enough pipeline stages on the BUFR that clocks the ISERDES to ensure that the data can be moved right to the boundary of the clock region, to be picked up by the other clock domain.
 
If the logic to process the data on the received clock is large (and hence requires more than one clock region), you are going to have to manually partition the block to logic on each of the two domains, which is done by choosing which clock clocks each section of the design. This will be quite inconvenient...
 
But, if you have to do this, it is doable - its just really time consuming...
 
Avrum
View solution in original post

A4，
时钟路径匹配在~500ps内（查看数据表）。
我们尽我们所能，但没有什么是完美的，过程，温度和电压变化都会增加任何偏差或差异。
我会尽量避免你画的东西，只通过一个全局缓冲区提供时钟。
如果可行且允许，BUFG将是最好的。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

a4,
 
Clock paths are matched to within ~ 500ps (check the data sheet).
 
We do the best we can, but nothing is perfect, and process, temperature, and voltage variations all add to any skew or difference.
 
I would try to avoid what you have drawn, and supply the clock through one global buffer, only.
 
A BUFG would be best, if available and if allowed.
 
Austin Lesea
Principal Engineer
Xilinx San Jose

如果处理得当，两个BUFR的输出是同相的。
但是你必须实现电路来同步BUFR计数器，这在UG472（v1.11.2，p.108）“BUFR Alignment”中有概述。
您需要在BUFMR上对输入时钟进行门控，重置两个BUFR，释放BUFR的复位，然后在BUFMR重新启用时钟 - 这可确保两个BUFR分频器同步，因此将具有相同的相位
（4个输入时钟边沿中的哪一个代表BUFR输出的上升沿）......
但...
管理这将很困难。
这些工具不会/不能将逻辑从一个BUFR移动到另一个BUFR。
就布局而言，这两个BUFR输出是独立的时钟。
无论你使用第一个时钟，你需要保留在BUFR的时钟区域，无论你使用第二个时钟区域，你的时钟都将在第二个时钟区域。
没有逻辑可以从一个区域移动到另一个区域。
因此，您的ISERDES将位于一个时钟区域。
如果所有结构逻辑都由另一个BUFR计时，那么ISERDES的输出将有很长的路由到达另一个时钟区域（可能会失败时序）。
为了避免这种情况，您必须确保在BUFR上有足够的流水线级，为ISERDES提供时钟，以确保数据可以直接移动到时钟区域的边界，由另一个时钟拾取
域。
如果处理接收时钟上的数据的逻辑很大（因此需要多个时钟区域），则必须在两个域中的每一个上手动将块分区为逻辑，这通过选择哪个时钟来完成
计时设计的每个部分。
这将非常不方便......
但是，如果你必须这样做，它是可行的 - 它只是非常耗时......
Avrum



以下为原文

If handled properly, the outputs of the two BUFRs are in phase. But you have to implement the circuit to synchronize the BUFR counters, which is outlined in UG472 (v1.11.2, p. 108) "BUFR Alignment". You need to gate the incoming clock at the BUFMR, reset the two BUFRs, release the reset of the BUFRs and then re-enable the clock at the BUFMR - this ensures that the two BUFR dividers are synchronized, and hence will have the same phase (which of the 4 input clock edges represents the rising edge of the BUFR output)...
 
BUT...
 
Managing this is going to be difficult. The tools will not/can not move logic from one BUFR to the other. As far as placer is concerned, these two BUFR outputs are separate clocks. Whatever you clock with the first one will need to remain in that BUFR's clock region, and whatever you clock with the 2nd one will be in the 2nd one's clock region. No logic will be able to be moved from one region to the other.
 
So, your ISERDESs will be in one clock region. If all the fabric logic is clocked by the other BUFR, then there will be long routes from the outputs of the ISERDES to reach the other clock region (which may fail timing). To avoid this, you are going to have to make sure that you have enough pipeline stages on the BUFR that clocks the ISERDES to ensure that the data can be moved right to the boundary of the clock region, to be picked up by the other clock domain.
 
If the logic to process the data on the received clock is large (and hence requires more than one clock region), you are going to have to manually partition the block to logic on each of the two domains, which is done by choosing which clock clocks each section of the design. This will be quite inconvenient...
 
But, if you have to do this, it is doable - its just really time consuming...
 
Avrum