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我正在为可能的网络应用程序评估Zynq-7020 SoC,我想知道延迟速度。 例如,对于数据包处理,使用现有的以太网接口,如果在PHY接口上接收到传入数据包,则需要多少时钟周期(或纳秒)才能将其放入RAM? 并且将这个数据包放入可编程逻辑电路需要多少纳秒? 或者,如果用大概的时间来回答要容易得多,那么对于1024字节的UDP数据包(包括IP / UDP报头)的简单回声,可以传输多少纳秒,比方说,我收到1个1024字节的数据包 ,然后我把它放到PL中,然后我把它变换掉,然后我把它放回PHY上,然后把它发送出去。 我应该期待几次? 纳秒? 还是微秒? 提前致谢。 以上来自于谷歌翻译 以下为原文 Hi, I am evaulating Zynq-7020 SoC for a possible networking application and I would like to know latency speeds. For example, for packet processing , using the existent Ethernet interface, if incoming packet is received on the PHY interface, how much clock cycles (or nanoseconds) would be needed to put it into RAM ? And how much nanoseconds would transcurr to put this packet into the programable logic circuit? Or if it is much easier to answer with an approximate time, how much nanoseconds would transcurr, for simple echo of the packet of an UDP packet of 1024 bytes (including IP/UDP header), lets say, I receive 1 packet of 1024 bytes, then I put it into PL, then I get it out transformed, then I put it back on the PHY, and send it out. What times should I expect? Nanoseconds? Or microseconds? Thanks in advance. |
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N,
10,100或1000 Mbs? (或更快) 只使用PS以太网,或者在PL中使用GT收发器? 运行什么软件? 对于广义性能,请参阅; ug1145 https://encrypted.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=5&ved=0ahUKEwintrWd2uvKAhUIxGMKHeRCBCUQFgg4MAQ&url=http%3A%2F%2Fwww。 xilinx.com%2Fsupport%2Fdocumentation%2Fsw_manuals%2Fxilinx2015_1%2Fug1145-SDK-系统performance.pdf&安培; USG = AFQjCNEPS ... Austin Lesea主要工程师Xilinx San Jose 以上来自于谷歌翻译 以下为原文 n, 10, 100, or 1000 Mbs? (or faster) Using only the PS ethernet, or using GT transceivers in the PL? Running what software? For generalized performance, see; ug1145 https://encrypted.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=5&ved=0ahUKEwintrWd2uvKAhUIxGMKHeRCBCUQFgg4MAQ&url=http%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Fsw_manuals%2Fxilinx2015_1%2Fug1145-sdk-system-performance.pdf&usg=AFQjCNEPS... Austin Lesea Principal Engineer Xilinx San Jose |
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1000 MB / s,或1千兆位。
这将是应用程序逻辑: 1.读取从PHY到RAM的数据包(这里也是问题,谁接收数据包?PL或PS?我想PS是因为它运行Linux并且有一个用于处理网络设备中断的中断请求向量,对吗? )如果数据包到达PL会很棒,那么每1字节数据就会有1个时钟周期? 2.将数据包从RAM移到PL中。 3.数据包处理逻辑(为简单起见,我们将数据包数据的位反转)这个时间取决于应用程序,如果时钟速度大约为700 MHZ,我可以自己计算它,它需要 5个时钟周期的操作,我们可以说这个时间将在3.5纳秒左右,这是正确的吗? 4.将数据包数据从PL移动到RAM 5.向内核发送一个系统调用来发送数据包并计算它花费的时间。 这是正确的流程,还是PL可以自己完成所有这些? 我只是不知道Zynq-7000如何在内部工作以及它能够做什么,这就是我要问的原因。 TIA Nulik 以上来自于谷歌翻译 以下为原文 1000 MB/s , or 1Gigabit. This would be the app logic: 1. Read the packet from PHY to RAM (also, here the question, who receives the packet? the PL or the PS ? I suppose the PS because it runs Linux and there is an interrupt request vector for handling network device interrupt, right?) If the packet comes to PL that would be awseome, that would be 1 clock cycle per 1 byte of data? 2. Move the packet from RAM into PL. 3. Do packet processing logic (for simplicity, lets say, we invert the bits of the packet data) This time depends on the app, and I can calculate it aproximately myself, if the clock speed is around 700 MHZ, and it would need 5 clock cycles for the operations, we could say this time will be around 3.5 nanoseconds, is that correct? 4. Move the packet data from PL to the RAM 5. Send the kernel a syscall to send the packet out and count the time it spends. Is this the correct flow , or the PL can do all this by itself? I just don't know how Zynq-7000 works internally and what is it capable to do, that is why I am asking. TIA Nulik |
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如果您在PL中执行了所有操作,您将获得更低且更一致的延迟。
但是,如果你使用像UDP这样的简单协议,那真的是可行的。 如果您正在进行完整的TCP / IP网络流量,那么您确实需要PS运行具有网络堆栈的操作系统。 但是,延迟将显着增加,只是为了使数据包进出内存,更不用说将数据包发送到PL或从PL进行处理所需的DMA。 以上来自于谷歌翻译 以下为原文 You would get much lower and more consistent latency if you did everything in the PL. But that's really only viable if you're using a simple protocol like UDP. If you're doing full TCP/IP network traffic then you really need the PS running an OS with network stack. But then the latency will increase significantly just to get packets into and out of memory, not to mention the DMAs required to send the packets to/from the PL for processing. |
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为简单起见,假设它不是UDP,而不是TCP,而不是IP,它是一个64字节大小的以太网帧。
什么是以纳秒为单位的近似时间,用于反转此类数据包中的位并将其发送回: - 仅使用PS - 仅使用PL - 使用PS将数据包数据传输到PL,反转这些位,将数据包返回到PS并使用PS将数据包发送到它来自哪里? 以上来自于谷歌翻译 以下为原文 for simplicity, lets say, it is not UDP, not TCP, not IP it is an ethernet frame, of 64 bytes in size. What would be an approximate time in nanoseconds to invert the bits in such packet and send it back with: - Using only PS - Using only PL - Using PS to transfer packet data to PL, invert the bits, return packet to PS and use PS to send the packet to where it came from? |
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我会说PL只有不到1us。
在PS运行linux时,就我而言,延迟是不确定的。 如果你运行裸机(没有操作系统,或者至少不是linux),你可以将它降低到不到10us,但是使用linux我认为它的范围可以从10us到100ms或更长,并且从包到 包。 拥有更多软件和Linux经验的人可能能够为您提供更准确的范围,但仅限PL的解决方案非常明确。 以上来自于谷歌翻译 以下为原文 I would say less than 1us with the PL only. With the PS running linux the latency is indeterminate as far as I'm concerned. If you ran bare metal (no OS, or at least not linux) you may be able to get it down to less than 10us, but with linux I think it could range from 10us to 100ms or longer, and that would vary from packet to packet. Someone with more software and linux experience may be able to give you a more accurate range, but the PL-only solution is pretty clear cut. |
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谢谢!
PL中不到1us是可以的。 我可以问这个简单测试使用多少逻辑单元? (近似) 关于PS时代,嗯,我能说什么,悲伤但是真实。 我将把最可能的逻辑放在PL中 以上来自于谷歌翻译 以下为原文 Thanks! Less than 1us in the PL is ok. How much logic cells would this simple test use , may I ask? (aprox) Regarding the PS times, well, what can I say, sad but true. I will be putting the most possible logic in the PL |
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