SPC560Bx ECC测试

你好凯文，
 
 
我已经向专家转发了这一点。
 
 最好的祝福
 
 二万



以下为原文





Hello Kevin ,


I have forwarded the point with Experts.

        Best Regards

                         Erwan

你好凯文，
 
 
从EEGR注入的ECC错误中恢复（1位情况）
我建议你使用矢量36（参见截图）。
 
并创建一个错误处理程序。
2位案例无法恢复，请使用向量35
 
你试过这个吗？
 
 最好的祝福
 
 二万



以下为原文





Hello Kevin ,


To recover  from an EEGR-injected ECC error (1 Bit case)
i recommend you to use the vector 36 (cf screenshot).

and to create an error handler.
2 Bit cases are not recoverable , use vector 35

Did you try this ?

   Best regards

                 Erwan

谢谢你的回复。
 
 要恢复内存位置需要写入然后读取以删除错误。
 问候
 凯文



以下为原文





Thanks for the response.

To recover the memory location needs to be written to and then read from to remove the error.
Regards
Kevin

关注问题：ECC错误是否会引发IVOR 01或IVOR 02异常？
 
 
 [编辑]当我们尝试清除ECC错误时，IVOR 1发生在我们的IVOR 2异常期间（因为在MSR中清除了EE），即当我们写入错误地址时发生另一个ECC错误。
 
 您能否告诉我们如何清除使用EEGR寄存器注入的错误（SPC560Bx参考手册的表524）？
 
 谢谢
 
 凯文



以下为原文





Follow on question: should an ECC error raise an IVOR 01 or an IVOR 02 exception?


[EDIT] The IVOR 1 occurs during our IVOR 2 exception (because EE is cleared in the MSR) when we try to clear the ECC error, i.e. another ECC error occurs when we write to the error address.  

Could you please tell us how to clear an error injected using the EEGR register (Table 524 of the SPC560Bx Reference Manual)?

Thanks

Kevin

我一直在努力。
 
 
 目前我们遇到的问题是，在电源循环后第一次运行时，我们的软件无法从ECC测试中恢复。如果我们重置软件（在UDE内），ECC测试将按预期工作。
 
 我们的测试工作如下：
 1）写入ECSM_EEGR寄存器（0x0100），该寄存器应在RAM中生成单个2位ECC错误。
 2）然后我们从ECSM_REAR获取错误的地址。
 3）然后我们将一些数据写入错误的地址。
 4）然后我们尝试从错误的地址读取。
 5）然后读取触发IVOR 02。
 6）然后我们清除ECSM_EEGR和ECSM_ESR
 7）然后我们通过写入然后读取它来恢复受影响的内存地址，这将恢复内存。
 8）然后我们从中断返回SRR0中的地址
 
 当电源立即运行软件时，软件会在上述步骤3中进入中断状态。它清除ECSM_EEGR和ECSM_ESR并返回到该行的代码，它然后再次尝试执行，但立即鼓动的IVOR 02.第二次到IVOR 02 ECSM_ESR和ECSM_EEGR在清零状态，表示没有任何ECC错误。当我们在IVOR 02中时，ESR（不是ECSM_ESR，异常综合症寄存器）具有以下位。 ST，VLEMI和XTE，其余都未设置。
 
 重置软件后，软件按上面写的顺序工作。然而，ESR（不是ECSM_ESR，异常综合症寄存器）具有以下位。 VLEMI和XTE。这意味着ST位仅在电源循环后在IVOR 02中设置，而不是在复位后。
 
 根据手册ST，存储操作是有意义的，因为中断在上电后写入命令而不是像复位后的读取命令那样触发。但是它列出了原因，如对齐，数据存储，数据TLB，程序。
 
 我希望你能解释为什么在重置后不同情况下中断发生的原因。如果还有任何其他问题我可以回答以帮助您了解这一点，我将非常愿意回答这些问题。



以下为原文





I've been working on this.


Currently we have the problem that our software will not recover from our ECC Test on the first run after a power cycle. If we reset the software (from within UDE) the ECC Test then works as expected.

Our test works as follows:
1) Write to the ECSM_EEGR register (0x0100) which should generate a single 2-bit ECC Error in RAM.
2) We then obtain the address of the error from the ECSM_REAR.
3) We then write some data to the address of the error.
4) We then attempt to read from the address of the error.
5) The read then triggers the IVOR 02.
6) We then clear the ECSM_EEGR and the ECSM_ESR
7) We then recover the affected memory address by writing then reading to it, this restores the memory.
8) We then return from Interrupt with the address in the SRR0

When running the software immediately from power on, the software goes to the interrupt on step 3 of the above. It clears the ECSM_EEGR and the ECSM_ESR and returns to that line of code, which it then tries to execute again but immediately instigates an IVOR 02. The second time into the IVOR 02 the ECSM_ESR and ECSM_EEGR are in a cleared state, indicating there is not any ECC errors. When we are in the IVOR 02 the ESR (Not the ECSM_ESR, the Exception Syndrome Register) has the following bits set. ST, VLEMI and XTE, the rest are not set.

After resetting the software, the software works in the order written above. However the ESR (Not the ECSM_ESR, the Exception Syndrome Register) has the following bits set. VLEMI and XTE. Meaning this ST bit is set in an IVOR 02 only after a power cycle and not after a reset.

According to the manual ST is a storage operation, which makes sense as the interrupt fires on a write command after power on and not on a read command like it does after a reset. However it lists the causes as alignment, data storage, data TLB, Program.

I'm hoping you can shed some light on why the interrupt fires on different occasions after a reset. If there are any other questions I can answer to help you get to the bottom of this I will be more than willing to answer them.

此外，手册中还说明了以下内容：
 
 
 ''对于两种类型的存储器（SRAM和闪存），目的是在数据期间产生错误
写循环，使得后续读取损坏的地址位置产生ECC
事件，单位校正或终止的双位不可校正错误
有错误响应。
 “”
 
 这意味着：
 1）EEGR已设定
 2）从REAR写入错误地址
 3）从错误地址读取（此处中断触发）
 
 我们遇到的问题是在电源循环后立即中断在写入时触发，这与手册相矛盾。



以下为原文





Additionally, the Manual says the following:


'' For both types of memories (SRAM and flash), the intent is to generate errors during data
write cycles, such that subsequent reads of the corrupted address locations generate ECC
events, either single-bit corrections or double-bit non-correctable errors that are terminated
with an error response.
''

Which implies that:
1) EEGR is set
2) Write to error address from REAR
3) Read from error address (Interrupt fires here)

Problem we are having is that immediately after a power cycle the interrupt is firing on the write, which contradicts the manual.