ADC处于扫描模式

在SAR ADC中存在一个可能影响模拟信号多路复用扫描的缺陷。等待下一个PSoC创作者发布或在赛普里斯发布一个案例，他们应该能够告诉你周围的工作。



     以下为原文
  There is a bug in SAR ADC which may affect mutiplexing scan of analog signal.  Wait for the next PSoC creator release or issue a case in Cypress, they should be able to tell you the work around.

这个bug可能不是你问题的根源，而是让你知道使用SAR ADC在使用多路复用器的扫描中存在一个问题。



     以下为原文
  That bug may not be the source of your problem, but just to let you know that there is a issue using SAR ADC in scanning using multiplexer.

你好。
感谢重播，我在哪里可以看到这个问题？



     以下为原文
  HI.
     
    thanks for the replay where can i see the issue?

我认为你应该想出一个解决当他们释放0soc创造者2。除非你是在赶时间，我建议你等待释放。



     以下为原文
   I thihk hey should come up with a fix when they release 0SoC creator 2. unless you are in a hurry, I suggest you wait for that release.

使用DMA最小CPU干预的ADC数据缓冲
这是我用PSoC3 Delsig ADC所做的事情之一。下面给出了同样的解释。我认为对于SAR ADC应该有类似的设计。
使用模拟硬件MUX扫描四个模拟通道，该多路复用器连接到ADC。ADC被配置为具有SoC终端。DMA配置数据从ADC outsamp登记转移到一些SRAM缓冲器。使用两个缓冲器来累积ADC数据。他们是填充顺序一前一后，在一个周期。两TDS相应地配置转移到上述缓冲液和被束缚。DMA传输是由ADC EOC的触发器发起的。DMA配置要求“每个爆裂”的请求，这个请求是由EOC ADC时有有效数据样本。在这种情况下，每个TD配置转换，ADC数×（4字节的地址复用器通道* ADC分辨率/ 8号）。AMUX通道每个ADC转换开关使用LUT，主频由EOC实现。EOC通过同步组件和同步bus_clk（这是非常高的）。一旦TD传输完成的termout信号触发中断设置一个标志来指示完成一个完整的扫描。下一个TD传输被启动并且进程继续。



     以下为原文
  
     
    This is one of things that I did with PSoC3 Delsig ADC. The explanation for the same is provided below. I think a similar design should be possible for SAR ADC.
    Four analog channels are being scanned using Analog Hardware Mux that is connected to ADC. ADC is configured to have SOC terminal. DMA is configured to transfer the data from ADC OUTSAMP register to some SRAM buffer. Two buffers are used to accumulate ADC data. And they are filled sequentially one after the other and in a cycle. Two TDs are configured accordingly to transfer to the above mentioned buffers and they are chained. The DMA transfer is initiated by a trigger from ADC EOC. DMA is configured to require a “request for every burst”, this request is provided by EOC of ADC when there is valid data sample available. Each TD in this case is configured to transfer, 4*number of Adc bytes (number of Amux channels* ADC resolution/8). The Amux channel switching for every ADC conversion is achieved using an LUT which is clocked by EOC. The EOC is passed through a SYNC component and synchronized to BUS_CLK(which is very high). Once a TD transfer is complete the termout signal triggers an ISR to set a flag to indicate complete of one complete scan. The next TD transfer is initiated and the process continues.

你好。
谢谢你的回放。
我试着用“EP645 60”这样做，但仍然有一个改变了另一个。
我在哪里可以看到这个问题的描述？
“U2”显示的是德尔塔西格玛，但我理解的问题是SAR。
谢谢。



     以下为原文
  hi .
     
    thanks for all your replays .
     
    i tried doing it somehow like in "EP64560" but still one measure changes the other.
    where can i see the discription of the issue?
    the exaple that is "U2" is showing is in delta sigma but as i understand the problem is with SAR.
    thanks.

我根据“EP645 60”的例子添加了我所做的。
一个措施影响另一个。



     以下为原文
  i have added what i did according to the "EP64560" example.
     
    one measure affects the other.

问题是只有SAR ADC。这个问题将不会出现如果ADC不用于多路输入。我们发现我们的项目开发过程中，需要一段时间才能有根源识别。修复很简单，但我这里没有。
例如如果你扫描4个通道和存储在一个数组中的adcdata [ 4 ]；
通过将所有输入固定到修复级别。选择任何一个频道（除了最后一个频道）。说如果你选择通道1，输入一个不同的层面上，看到你在adcdata [ 1 ]所示的新值（即通道2登记）。如果是这样的话，你会受到这个问题的影响。然而，如果它改变了正确的adcdata [ 0 ]，比你不受影响。
如果你受到影响，创造一个案例和柏树应该能够识别如果修复工程与您的应用程序。



     以下为原文
  The issue is with SAR ADC only. The problem will not show up if the ADC is not used for multiplex input. We found it during our project development and takes a while to have the root source identifed. The fix is simple, but I do not have it here. 
    For example if you scan 4 channels and store in in an array ADCdata[4];
    By fixing all input to a fix level. pick any one channel (except the last one). Say if you pick channel 1, input a different level, see you the new value shown in ADCdata[1] (ie the register for channel 2). if that is that case, you are affected by this problem. However, if it changes correctly in ADCdata[0], than you are not affected.
    If you are affected, create a case and Cypress should be able to identify if the fix works with your application.

你好。
谢谢你的回放。
你所描述的正是我们的问题。
我在赛普里斯见过阿卡斯，但没有回应。
你能告诉我你有什么安排吗？



     以下为原文
  hi.
     
    thanks for your replay .
     
    what you described is exactly our problem.
    i have opend acase in Cypress but no responce yet.
     
    can you tell me what was the Fix for you?

尝试以下
*在初始化程序*//*中执行此操作，只需在ADC*Stc**之后执行一次。
/*启动ADC*/ADCYSTART（）；AdcSARARCCS00Reg＝AdcSARA ReSeTyStftAcAc能能能活泼；CyDelayUs（2）；AdcSalaCs00Reg；
干杯



     以下为原文
  Try the following
    /* Do this in your initialization routine */
/* you only need to do it once after ADC_Start */
     /* Start the ADC */
 ADC_Start();
 ADC_SAR_CSR0_REG |= ADC_SAR_RESET_SOFT_ACTIVE;
 CyDelayUs(2);
 ADC_SAR_CSR0_REG &= ~ADC_SAR_RESET_SOFT_ACTIVE;
    Cheers