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我有一个设计与以下heirarchy - 顶层 .. module1 ..module2 .....单词数 module3有一个名为“link”的4位输入寄存器,我需要忽略它的时序(因为这个寄存器没有动态改变)。 在我的ucf中,我尝试了以下语法,但似乎都没有。 对于以下,我总是得到错误 - ....不匹配任何设计对象(约束系统58错误) NET“top_level / module2 / module3 / link ”tiG; NET“module2 / module3 / link ”TIG; NET“module2 / module3 / link ”TNM_NET =“fp1”; TIMESPEC“TS_fp1”=来自“fp1”TIG; 确实没有标记错误的约束是 - INST“module2 / module3 / link ”TIG; 我的问题是 - 1)是否有任何特殊的语法来指定设计层次内部的网络上的TIG? 2)是否有任何依赖天气的内部线/ reg或模块输入/输出? 3)如果我的设计输入是edif文件,上述内容是否会工作? 4)在什么情况下我应该使用INST,在什么情况下我应该使用NET? 帮帮我!!! 以上来自于谷歌翻译 以下为原文 hi, i have a design with the following heirarchy - top_level .. module1 ..module2 .....module3 module3 has an 4 bit input register called "link" on which i need to ignore the timing (because this reg is not changed dynamically). in my ucf, i've tried the following syntaxes but none seem to work. for the following, i always got the error - .... does not match any design object (constraint system 58 error) NET "top_level/module2/module3/link" TIG; NET "module2/module3/link" TIG; NET "module2/module3/link" TNM_NET = "fp1"; TIMESPEC "TS_fp1" = from "fp1" TIG; the constraint that does go through without flagging an error is - INST "module2/module3/link" TIG; my questions are - 1) is there any special syntax to specify a TIG on a net that is deep inside the design heirarchy? 2) is there any dependency on weather it is an internal wire/reg or module input/output? 3) if my design input is an edif file, will the above constriants till work? 4) in what case should i use INST and in what case should i use NET? HELP!!! |
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喜
为您的案例应用约束的更简单方法是使用约束编辑器。 请参阅http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/pce_p_exceptions_ignore_paths.htm 请参阅本主题,了解INST和NEThttp://forums.xilinx.com/t5/Timing-Analysis/NET-vs-INST/td-p/218287之间的区别 --hem -------------------------------------------------- --------------------------------------------请注意 - 请注明 如果提供的信息有用,请回答“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢K-- -------------------------------------------------- --------------------- 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 hi, the easier way to apply constraint for your case is to use constraints editor. refer to http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/pce_p_exceptions_ignore_paths.htm refer to this topic for difference between INST and NET http://forums.xilinx.com/t5/Timing-Analysis/NET-vs-INST/td-p/218287 --hem ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ----------------------------------------------------------------------------------------------View solution in original post |
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喜
为您的案例应用约束的更简单方法是使用约束编辑器。 请参阅http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/pce_p_exceptions_ignore_paths.htm 请参阅本主题,了解INST和NEThttp://forums.xilinx.com/t5/Timing-Analysis/NET-vs-INST/td-p/218287之间的区别 --hem -------------------------------------------------- --------------------------------------------请注意 - 请注明 如果提供的信息有用,请回答“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢K-- -------------------------------------------------- --------------------- 以上来自于谷歌翻译 以下为原文 hi, the easier way to apply constraint for your case is to use constraints editor. refer to http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/pce_p_exceptions_ignore_paths.htm refer to this topic for difference between INST and NET http://forums.xilinx.com/t5/Timing-Analysis/NET-vs-INST/td-p/218287 --hem ---------------------------------------------------------------------------------------------- Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful. Give Kudos to a post which you think is helpful and reply oriented. ---------------------------------------------------------------------------------------------- |
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只有当我将它应用于RTL中的reg时,才会传递时间忽略/错误路径约束。
但是,当我尝试将其应用于驱动reg的导线时,TIG约束会标记错误。 那么我们只能将TIG应用于“钟表”元素吗? 如果我想忽略一条线......或者输入/输出端口,那么从时间上看,我应该使用什么约束? 以上来自于谷歌翻译 以下为原文 the timing ignore/false path constraints pass only when i apply it to a reg in my RTL. however when i try and apply it to a wire which is driving the reg, then the TIG constraint flags an error. so is it that we can only apply TIG to "clocked" elements? if I want to ignore a wire ... or an input/output port for that matter, from timing, what is the constraint i should use? |
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嗨,TIG可以在NETS,PINS和INSTANCES上申请。请参阅http://www.xilinx.com/cn/itp/xilinx10/books/docs/cgd/cgd.pdf谢谢,Yash
以上来自于谷歌翻译 以下为原文 Hi, TIG can be apply on NETS, PINS and INSTANCES. Refer http://www.xilinx.com/itp/xilinx10/books/docs/cgd/cgd.pdf Thanks, Yash |
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是的...约束编辑器比直接在UCF中指定网络更容易...尤其是如果你使用synplify ...那么如果你试图约束设计,网名就会改变。
所以约束编辑器是一个更好的选择 以上来自于谷歌翻译 以下为原文 yup ... the constraints editor was way easier than specifying the nets in the UCF directly ... esp if you use synplify ... then if you try and constrain the design, the net names change. so constraints editor is a better option |
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