Kintex 7的最高工作频率是？

嗨，
设计的Fmax取决于所使用资源的最大规格，如缓冲区，时钟模块，编码，路由等。
您可以实施设计和检查时间报告。
还运行IBIS smluations来检查SI。
另请参阅Kintex -7的数据表，了解电气规格和开关特性
http://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf
通过相关讨论获得更多输入和链接
http://forums.xilinx.com/t5/Design-Entry/how-to-find-the-maximum-frequency-of-a-design/td-p/25687
http://forums.xilinx.com/t5/Digital-Signal-Processing-IP-and/fmax-CLOCK-FREQUENCY-for-XC7K160T-1FFG676I/td-p/551057
希望这可以帮助
-Vanitha
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在原帖中查看解决方案



以下为原文

Hi,
 
Fmax of design depends on max specifications of  resources used like buffers, clocking modules, how well you code, routing etc.
You can implement your deisgn and check timing reports.
Also run IBIS smluations to check the SI.
 
Also go through data sheet of Kintex -7 for electrical specifications and switching charateristics 
http://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf
 
Go through relavant discussions for more inputs and links
http://forums.xilinx.com/t5/Design-Entry/how-to-find-the-maximum-frequency-of-a-design/td-p/25687
 
http://forums.xilinx.com/t5/Digital-Signal-Processing-IP-and/fmax-CLOCK-FREQUENCY-for-XC7K160T-1FFG676I/td-p/551057
 
 
Hope this helps
 
-Vanitha
---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented
View solution in original post

嗨，
设计的Fmax取决于所使用资源的最大规格，如缓冲区，时钟模块，编码，路由等。
您可以实施设计和检查时间报告。
还运行IBIS smluations来检查SI。
另请参阅Kintex -7的数据表，了解电气规格和开关特性
http://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf
通过相关讨论获得更多输入和链接
http://forums.xilinx.com/t5/Design-Entry/how-to-find-the-maximum-frequency-of-a-design/td-p/25687
http://forums.xilinx.com/t5/Digital-Signal-Processing-IP-and/fmax-CLOCK-FREQUENCY-for-XC7K160T-1FFG676I/td-p/551057
希望这可以帮助
-Vanitha
--------------------------------------------------
-------------------------------------------请在发布前进行谷歌搜索，
您可能会找到相关信息。请留下帖子 - “接受为解决方案”，如果提供的信息有用且回复，请给予赞誉



以下为原文

Hi,
 
Fmax of design depends on max specifications of  resources used like buffers, clocking modules, how well you code, routing etc.
You can implement your deisgn and check timing reports.
Also run IBIS smluations to check the SI.
 
Also go through data sheet of Kintex -7 for electrical specifications and switching charateristics 
http://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf
 
Go through relavant discussions for more inputs and links
http://forums.xilinx.com/t5/Design-Entry/how-to-find-the-maximum-frequency-of-a-design/td-p/25687
 
http://forums.xilinx.com/t5/Digital-Signal-Processing-IP-and/fmax-CLOCK-FREQUENCY-for-XC7K160T-1FFG676I/td-p/551057
 
 
Hope this helps
 
-Vanitha
---------------------------------------------------------------------------------------------
Please do google search before posting, you may find relavant information.
Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented

是的，不是答案！
我有一个800 MHz的knitex runnig的PLL， 
但是你在那个时间里做不了多少，时间是1.2 ns，
整个芯片的适应性是几纳秒的顺序， 
所以，是的，你可以获得800 MHz的FF，但不要期望通过DSP和芯片获得数据。
作为参考，对于所有常见的空穴，-2部分的相对数将是250MHz，而没有太多问题。 
但是知道，具体的'我的未经验证的设计可以在800 MHz运行'。



以下为原文

yes and no is the answer !
 
I have the PLL in a knitex runnig at 800 MHz, 
   but you cant get much done in that time, period is 1.2 ns,
 
the propergation across the chip is of the order a few ns, 
   so yes, you can get a FF togling at 800 MHz, but don't expect to get data through a DSP and across the chip.
 
For reference, with all the usual caviates, relaistic  number for a -2 part would be 250 MHz, withotu too much problems.
   buta specific 'can my unsepcified design run at 800 MHz,' , who know.
 
 
 
      

嗨Vanitha，
在器件的DC特性中，提到了BUFG，BUFH等的一些数字。
但我有一个混乱，这意味着FPGA架构无法在上述数字之上运行，或者数据无法从这些数字之外的FPGA中取出。
再次在同一数据表中提到MMCM可以产生最大时钟或933MHz。
我不明白FPGA是否不支持这样的频率，那么MMCM为什么以及如何能够产生这样的频率时钟。



以下为原文

Hi Vanitha,
 
In the DC characteristics of the device some figures for BUFG, BUFH etc are mentioned. But I have a confusion that does it mean that FPGA fabrics can't be run above the mentioned figures or data can't be taken out of the FPGA above these figures. Again in the same datasheet it is mentioned that MMCM can produce max clock or 933MHz. I didn't understand if the FPGA does not support such frequencies, then why and how the MMCM is able to produce such a frequency clocks.

现在你进入了细节。
这完全取决于FPGA的不同部分。
以你的MMCM为例。 
这是裸片的一部分，它周围有外围设备来制作时钟。 
因此，MMCM的振荡器部分/分频器/延迟元件被设计为快速运行。 
这样一个人就可以说一个100 MHz的时钟，将它乘以8并除以7，得到114.Mhz时钟。 
114 MHz时钟可以在芯片周围发送，而MMCM的800 MHz则不能。 
面料不会让它。
像IO serdes这样的东西比SRL移位寄存器运行得更快，
如果你有一个多瓦片部分，那么人们会发现瓦片之间的链接比硅片上的链接慢。
FPGA中最古老的问题是“我能以多快的速度运行”， 
它是最古老的问题，必须设计芯片才能知道， 
它是如何用FPGA设计的全部内容。 
好玩啊。
这就是为什么我们得到这么多的报酬！



以下为原文

Now your into the nitty grity .
 
Its all about what different parts of the FPGA are for.
 
take your example about the MMCM.
   That is a part of the die, that has peripherals around it to produce clocks.
       As such the oscilator part / the dividers / the delay elements of the MMCM are designed to run fast.
    
That way one can put in say a 100 MHz clock, multiply it by say 8 and divide by 7,to give a 114. Mhz clock.
        the 114 MHz clock can be sent around the chip, the 800 MHz of the MMCM can't. 
             the fabric just wont let it.
 
Things like IO serdes can run faster than SRL shift registers,
 
If you have a multi tile part, Then one finds the links between tiles are slower than links on the silicon., as one would expect.
 
The oldest question in FPGAs is 'how fast can I get it to run', 
    and its the oldest problem, one has to design with the chip to know, 
 
    
Its all part of how one designs with an FPGA. 
  Fun ah. 
 
thats why we get paid so much !
 
 

嗨drjohnsmith，非常感谢你的回复和清除我的怀疑。
但我还想知道更多的事情......实际上在我的设计中，我的Fmax为300M，设计的一部分时钟为800M（设计有三个时钟40M，160M，和800M），现在我好了
将不得不将其减少到640M，但我认为还会有时间问题......对吗？
你能告诉我如何提高设计的性能......任何参考文件???



以下为原文

Hi drjohnsmith,

Thanks a lot for reply and clearing my doubts. But still I want to know one more thing ... actually in my design I am getting Fmax as 300M and a part of the design has to clocked at 800M(design has three clocks 40M, 160M, & 800M ), well now I will have to reduce it to 640M, but still I think there will be timing problem ... right? Could you please tell me how to increase the performance of the design ... any reference document ???

通过并行执行更多操作，可以提高设计的性能，
老人
如果一个人需要10天才能挖一条沟，那么10个人需要多长时间才能挖出同样大小的沟，
回答1天，（假设你不像我的女儿那样聪明，因为已经被挖了就回答零）



以下为原文

One increases the performanc of a design by doing more in parallel,
 
the old
 
if it takes one person 10 days to dig a trench, how long will it take 10 people to dig the same size trench,
 
answer 1 day, ( assuming your not being clever like my daughter was and answer zero as its already been dug )