如何解决通用Xilinx FPGA DSP片和逻辑单元上的问题？

嗨Z.
1）否，DSP切片不计入正常的LUT /寄存器报告中。
它们是完全分开的
2）绝对！
你可以用它们做任何事情。
他们非常灵活。
我建议为该片段阅读相关的UG以更好地了解其功能。
你提到了Virtex 5中的DSP48E：
http://www.xilinx.com/support/documentation/user_guides/ug193.pdf
www.xilinx.com



以下为原文

Hi Z.
 
1) No, DSP slices are not counted in the normal LUT/register reports. They are totally separate
2) Absolutely! You can use them for anything. They are very flexible. I recommend reading the relevant UG for that slice to get a better idea of the capabilities. You mention DSP48E which was in Virtex 5:
http://www.xilinx.com/support/documentation/user_guides/ug193.pdf
www.xilinx.com

感谢您的投入。
我将通过文档。
你提到我们也可以在DSP48E Slice中实现常规逻辑。
我只需要对这方面做一些澄清。
我在fpga上做的设计，如果他们没有特定的多/添加类型的操作，那么在这种情况下，我通常看到dsp48E切片在设计摘要中具有0％的利用率。
那么我们是否需要专门指导ISE工具使用DSP48E切片来实现“常规”逻辑或者ISE工具是否自行决定？
或者 - 在什么情况下，该工具是否决定使用DSP48E来实现常规逻辑？
请告诉我 ...
谢谢，
ž。



以下为原文

thanks for the inputs. i will go through the doc.
 
you mention that we can implement regular logic in the DSP48E slice as well. i just needed some clarification on that aspect.
 
the designs i've made on fpga, if they dont have a specific mult/add type of operation, then in that case, i've generally seen the dsp48E slice to have 0% utilization in the design summary.
 
so do we need to specifically guide the ISE tool to use DSP48E slices to implement "regular" logic or does the ISE tool decide itself? 
 
or - under what case, does the tool decide it will use DSP48E to implement regular logic as well?
 
please let me know ...
 
thanks,
z.
 

你好，
有关该信息，请参阅XST用户指南：
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst_v6s6.pdf
具体来说，第7章解释了综合工具如何推断在什么条件/编码风格下使用什么结构。
一般来说，XST主要只推断乘法器，加法器，累加器/计数器等。如果你想做按位逻辑，多路复用器，比较器，SIMD模式等，那么你需要实例化原语或使用类似DSP的IP
核心中的宏。
www.xilinx.com



以下为原文

Hello,
 
For that information, you should refer to the XST user guide:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/xst_v6s6.pdf
 
Specifically, Chapter 7 explains how the synthesis tool infers what structure to use under what conditions/coding styles.
 
In general, XST will mostly only infer multipliers, adders, accumulators/counters, etc. If you want to do bitwise logic, muxes, comparators, SIMD mode, etc, then you will need to instantiate the primitive or use an IP like the DSP Macro in coregen.
 
www.xilinx.com

>>）绝对！
你可以用它们做任何事情。
它们非常灵活。我喜欢dsp48块，但我不会那么远。
最重要的是，你不能用它们实现LUT。
添加/子（SIMD或其他），模式检测，移位器，宽xor都可以。
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以下为原文

>> ) Absolutely! You can use them for anything. They are very flexible.

I like dsp48 block but I wouldn't go that far. Most importantly you can not implement a LUT with them. add/sub (SIMD or otherwise), pattern detection, shifter, wide xor are ok though.
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是的，好的一点。
该声明有点误导。
谢谢你抓住我！
更确切地说，我应该说“你可以将它们用于除了mult / add之外的许多通用逻辑需求。”
www.xilinx.com



以下为原文

Yeah, good point. That statement was a little misleading. Thanks for catching me!
 
To be more precise, I should have said that "you can use them for many of your generic logic needs beyond mult/add."
www.xilinx.com

1）DSP48E切片是整个切片数量的一部分还是它们在FPGA上共享资源？
我的答案是否定的。
这些是硬块，并且能够以多少方式进行混淆。
它始于48个diffrenent配置，这就是为什么它被称为dsp48，现在这个块功能超过100个
2）如果我们没有进行任何DSP操作，那么DSP48E Slice是否可以用于实现某些常规逻辑，或者这些DSP Slice是否专门用于实现DSP（mult / carry-add）类型的操作？
工具将照顾dsp48切片它会在需要时推断dsp48取决于你的逻辑。
您可以查看综合和实施报告
谢谢和RegardsBalkrishan -----------------------------------------------
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以下为原文

1) are the DSP48E slices part of the overall slice count or are they seperate resources on the FPGA alltogether?
I am answer is No as well . These are the hard  block and able to confgirue in the number of way . It was started with 48 diffrenent configuration thats why its called dsp48 , Now this block capble of more than 100 functions
2) if we are not doing any DSP operation, then can the DSP48E slices be used to implement some regular logic or are these DSP slices specifically for implementing DSP (mult/carry-add) type of operations only?.
 
tool will take care for dsp48 slice it will infer dsp48 whenever it needed depends upon you logic. You may look into synthesis ans implementations reports
Thanks and Regards
Balkrishan
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