通过PLB总线对DDR内存的IP核rd/wr请求不会返回任何响应

你好！
我是这个FPGA设计的初学者，尤其是使用EDK工具。
我正在尝试将新IP集成到演示EDK设计中;
它应该使用PLB总线与DDR2通信。
我正在使用“创建或导入外围设备”WIzard来生成这个新的IP核（具有主接口和从接口）并根据生成的user_logic模块中的指令进行修改。
事实是我没有收到来自总线的任何信号（这让我担心，因为我的主人正在启动rd_from_memory动作 - 断言相应的信号 - 并等待确认 - 从未发生过）。
所有这些都使用PLB总线。
我不想使用microblaze，只是想将它保存在硬件中而不将其导出到SDK for SW使用​​。
有没有人知道我没有从公交车上收到任何东西的原因？
我的user_logic代码的一部分可以在下面找到：
参数X_RES = 1280;
参数Y_RES = 720;
参数NO_OF_PIXEL_PER_DATA = 16;
// 2 ^ x = 16 => x = 4
参数NO_OF_DATA_PER_ADDR = C_MST_DWIDTH >> 4;
参数NO_OF_ADDR_TO_WRITE =（X_RES * Y_RES）>> NO_OF_DATA_PER_ADDR;
参数BASE_ADDR_TO_READ = 32'h50000000;
参数BASE_ADDR_TO_WRITE = 32'h49000000;
reg [0：C_MST_AWIDTH-1] rd_addr_reg，rd_addr_next;
reg [0：C_MST_AWIDTH-1] wr_addr_reg，wr_addr_next;
reg [0：C_MST_AWIDTH-1] incr_reg，incr_next;
reg [0：C_MST_DWIDTH-1] data_reg，data_next;
reg [0：1] state_reg，state_next;
reg [0：5] LED_reg，LED_next;
总是
@（posedge Bus2IP_Clk）
开始
if（Bus2IP_Reset）
开始
rd_addr_reg
非常感谢你！



以下为原文

Hello!

I am a beginner in this FPGA design and especially in using the EDK tool.
I am trying to integrate a new IP into a demo EDK design; it is supposed to communicate with the DDR2 using a PLB bus. I am using the "Create or Import Peripheral" WIzard to generate this new IP Core (having both master and slave interfaces) and modifying it according to the instructions in the generated user_logic module. The fact is that I don't receive any signals from the bus (which worries me because my master is initiating the rd_from_memory action -asserting corresponding signals - and waits for the acknowledge - which never comes). And all these using the PLB bus.

I don't want to use microblaze, just want to keep this in hardware without exporting it to SDK for SW usage.

Has anyone any idea about the reason for which I do not receive anything from the bus?

Part of my user_logic code can be found below:

        parameter X_RES= 1280;parameter Y_RES = 720;parameter NO_OF_PIXEL_PER_DATA= 16; // 2^x = 16 => x = 4parameter NO_OF_DATA_PER_ADDR= C_MST_DWIDTH >> 4;parameter NO_OF_ADDR_TO_WRITE= (X_RES * Y_RES) >> NO_OF_DATA_PER_ADDR;parameter BASE_ADDR_TO_READ= 32'h50000000;parameter BASE_ADDR_TO_WRITE= 32'h49000000;reg [0: C_MST_AWIDTH-1] rd_addr_reg, rd_addr_next;reg [0: C_MST_AWIDTH-1] wr_addr_reg, wr_addr_next;reg [0: C_MST_AWIDTH-1] incr_reg, incr_next;reg [0: C_MST_DWIDTH-1] data_reg, data_next;reg [0 : 1] state_reg, state_next;reg [0 : 5] LED_reg, LED_next;always@(posedge Bus2IP_Clk)beginif ( Bus2IP_Reset )beginrd_addr_reg <= BASE_ADDR_TO_READ;wr_addr_reg<= BASE_ADDR_TO_WRITE;incr_reg <= NO_OF_ADDR_TO_WRITE;LED_reg<= 1'b0;state_reg <= 0;data_reg<= 0;endelsebeginrd_addr_reg <= rd_addr_next;wr_addr_reg<= wr_addr_next;incr_reg <= incr_next;LED_reg<= LED_next;state_reg <= state_next;data_reg<= data_next;endendreg IP2Bus_MstWr_Req_reg, IP2Bus_MstWr_Req_next;reg IP2Bus_MstRd_Req_reg, IP2Bus_MstRd_Req_next;reg [0 : C_MST_DWIDTH/8-1]  IP2Bus_Mst_BE_reg, IP2Bus_Mst_BE_next;reg [0 : C_MST_DWIDTH-1]IP2Bus_MstWr_d_reg, IP2Bus_MstWr_d_next;reg [0 : C_MST_AWIDTH-1]IP2Bus_Mst_addr_reg, IP2Bus_Mst_addr_next;always @(posedge Bus2IP_Clk)beginif ( Bus2IP_Reset )beginIP2Bus_MstWr_Req_reg<= 1'b0;IP2Bus_MstRd_Req_reg<= 1'b0;IP2Bus_MstWr_d_reg<= 0;IP2Bus_Mst_addr_reg<= 0;IP2Bus_Mst_BE_reg<= 0;endelsebeginIP2Bus_MstWr_Req_reg <= IP2Bus_MstWr_Req_next;IP2Bus_MstRd_Req_reg<= IP2Bus_MstRd_Req_next;IP2Bus_MstWr_d_reg<= IP2Bus_MstWr_d_next;IP2Bus_Mst_addr_reg<= IP2Bus_Mst_addr_next;IP2Bus_Mst_BE_reg<= IP2Bus_Mst_BE_next;endendalways@(*)beginincr_next = incr_reg;rd_addr_next = rd_addr_reg;wr_addr_next = wr_addr_reg;LED_next = LED_reg;state_next = state_reg;data_next = data_reg;IP2Bus_MstWr_Req_next = 1'b0;IP2Bus_MstRd_Req_next = 1'b0;IP2Bus_Mst_addr_next = IP2Bus_Mst_addr_reg;IP2Bus_MstWr_d_next = IP2Bus_MstWr_d_reg;IP2Bus_Mst_BE_next = IP2Bus_Mst_BE_reg;if (RD_WR)begincase (state_reg)0:beginstate_next = 1;end1:begin //first clock = read one data cycleIP2Bus_MstRd_Req_next = 1'b1;IP2Bus_Mst_BE_next = 4'b1111;if ( Bus2IP_Mst_CmdAck )begin// suppose each Byte Enable is set to a logic "1" Bus2IP_BEIP2Bus_Mst_addr_next = rd_addr_reg;data_next = Bus2IP_MstRd_d;IP2Bus_MstRd_Req_next = 1'b0;IP2Bus_Mst_BE_next = 4'b0000;state_next = 2;end/*IP2Bus_Data,                    // IP to Bus data busIP2Bus_RdAck,                   // IP to Bus read transfer acknowledgementIP2Bus_WrAck,                   // IP to Bus write transfer acknowledgementIP2Bus_Error,                   // IP to Bus error responseIP2Bus_MstRd_Req,               // IP to Bus master read requestIP2Bus_MstWr_Req,               // IP to Bus master write requestIP2Bus_Mst_Addr,                // IP to Bus master address busIP2Bus_Mst_BE,                  // IP to Bus master byte enablesIP2Bus_Mst_Lock,                // IP to Bus master lockIP2Bus_Mst_Reset,               // IP to Bus master reset*/end2:begin //second clock = write the read dataIP2Bus_MstWr_d_next = data_reg;IP2Bus_Mst_addr_next = wr_addr_reg;IP2Bus_MstWr_Req_next = 1'b1;if ( Bus2IP_Mst_CmdAck )state_next = 2;end3: beginrd_addr_next = rd_addr_reg + 1'b1;wr_addr_next = wr_addr_reg + 1'b1;if ( rd_addr_reg == NO_OF_ADDR_TO_WRITE + BASE_ADDR_TO_READ)beginLED_next = ~LED_reg;rd_addr_next = BASE_ADDR_TO_READ;wr_addr_next = BASE_ADDR_TO_WRITE;endstate_next = 0;endendcaseendendassign LED[0] = IP2Bus_MstRd_Req_reg;assign LED[1] = Bus2IP_Mst_CmdAck;assign LED[2] = Bus2IP_Reset;assign LED[3:4] = state_reg;assign LED[5] = RD_WR;assign IP2Bus_Mst_Addr = IP2Bus_Mst_addr_reg;//read signalsassign IP2Bus_MstRd_Req = IP2Bus_MstRd_Req_reg;assign IP2Bus_Mst_BE = IP2Bus_Mst_BE_reg;assign IP2Bus_Mst_Lock = 1'b0;assign IP2Bus_Mst_Reset = 1'b0;//write signalsassign IP2Bus_MstWr_d = IP2Bus_MstWr_d_reg;assign IP2Bus_MstWr_Req = IP2Bus_MstWr_Req_reg;
Thank you very much!