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下面的代码取自着名的Pong Chu书籍FPGA Prototyping VHDL示例（我修改了复位信号并使其同步）。
它合成了1个BRAM但是发出了警告。
警告：Xst：3211 - 不能将Block RAM资源用于信号。
请检查是否同步读取RAM内容。
我用谷歌搜索，在xilinx论坛找到一个帖子但不是答案。
http://forums.xilinx.com/t5/7-Series-FPGAs/Xst-3211-Cannot-use-block-RAM-resources-for-signal-lt-Mram/td-p/370747
bbinb
------------------------
库IEEE;使用IEEE.STD_LOGIC_1164.ALL;使用IEEE.NUMERIC_STD.ALL;
entity uart_rx isgeneric（DBIT：integer：= 8; SB_TICK：integer：= 16）; port（clk，rst：in std_logic; rx：in std_logic; s_tick：in std_logic; rx_done_tick：out std_logic; dout：out std_logic_vector（7 downto）
0））;结束uart_rx;
架构uart_rx的行为是
type state_type是（idle，start，data，stop）; signal state_reg，state_next：state_type; signal s_reg，s_next：unsigned（3 downto 0）; signal n_reg，n_next：unsigned（2 downto 0）; signal b_reg，b_next：std_logic_vector
（7 downto 0）;
属性fsm_style：string; state_reg的属性fsm_style：signal是“bram”;
开始
--FSMD state＆amp;
data registersprocess（clk）beginif（clk'event and clk ='1'）then if（rst ='1'）then state_reg s_reg'0'）;
n_reg'0'）;
b_reg'0'）;
else state_reg s_reg n_reg b_reg end if;
结束如果;结束过程;
--process（clk，rst）--begin--- if（rst ='1'）then-- state_reg - s_reg'0'）; - n_reg'0'）; - b_reg'0'）
; - elsif（clk'event和clk ='1'）然后 - state_reg - s_reg - n_reg - b_reg - 结束if; - - end process;
- 下一状态逻辑＆amp;
数据路径功能单元/ routingprocess（state_reg，s_reg，n_reg，b_reg，s_tick，rx）begin state_next s_next n_next b_next rx_done_tick case state_reg is idle => if（rx ='0'）then state_next s_next'0'）;
万一;
当start => if（s_tick ='1'）时，如果s_reg = 7则state_next s_next'0'）;
n_next'0'）;
否则s_next结束if;
万一;
当data => if（s_tick ='1'）时，如果s_reg = 15则s_next'0'）;
b_next if n_reg =（DBIT - 1）then state_next else n_next end if;
否则s_next结束if;
万一;
当stop => if（s_tick ='1'）时，如果s_reg =（SB_TICK - 1）则state_next rx_done_tick else s_next end if;
万一;
结束案例;
结束过程;
dout 以下为原文
I tried different process blocks approach for next state logic. The code below is taken from famous Pong Chu book FPGA Prototyping VHDL Examples (I modified reset signal and made it synchronous). It synthesize 1 BRAM but gives that warning.
WARNING:Xst:3211 - Cannot use block RAM resources for signal
I googled it, find a thread in xilinx forum but not an answer.
http://forums.xilinx.com/t5/7-Series-FPGAs/Xst-3211-Cannot-use-block-RAM-resources-for-signal-lt-Mram/td-p/370747
bbinb
------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity uart_rx is
generic (
DBIT : integer := 8;
SB_TICK : integer := 16
);
port (
clk, rst : in std_logic;
rx : in std_logic;
s_tick : in std_logic;
rx_done_tick: out std_logic;
dout : out std_logic_vector (7 downto 0)
);
end uart_rx;
architecture Behavioral of uart_rx is
type state_type is (idle, start, data, stop);
signal state_reg, state_next : state_type;
signal s_reg , s_next : unsigned (3 downto 0) ;
signal n_reg , n_next : unsigned (2 downto 0) ;
signal b_reg , b_next : std_logic_vector (7 downto 0 ) ;
attribute fsm_style : string;
attribute fsm_style of state_reg : signal is "bram";
begin
--FSMD state & data registers
process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
state_reg <= idle;
s_reg <= (others => '0') ;
n_reg <= (others => '0') ;
b_reg <= (others => '0') ;
else
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
end if;
end if;
end process;
--process (clk,rst)
--begin
--
-- if (rst = '1') then
-- state_reg <= idle;
-- s_reg <= (others => '0') ;
-- n_reg <= (others => '0') ;
-- b_reg <= (others => '0') ;
-- elsif (clk'event and clk = '1') then
-- state_reg <= state_next;
-- s_reg <= s_next;
-- n_reg <= n_next;
-- b_reg <= b_next;
-- end if;
--
--end process;
-- next-state logic & data path functional units/routing
process (state_reg, s_reg, n_reg, b_reg, s_tick, rx)
begin
state_next <= state_reg;
s_next <= s_reg;
n_next <= n_reg;
b_next <= b_reg;
rx_done_tick <= '0';
case state_reg is
when idle =>
if (rx = '0') then
state_next <= start;
s_next <= (others => '0');
end if;
when start =>
if (s_tick = '1') then
if s_reg = 7 then
state_next <= data;
s_next <= (others => '0');
n_next <= (others => '0');
else
s_next <= s_reg + 1;
end if;
end if;
when data =>
if (s_tick = '1') then
if s_reg = 15 then
s_next <= (others => '0');
b_next <= rx & b_reg(7 downto 1);
if n_reg = (DBIT - 1) then
state_next <= stop;
else
n_next <= n_reg + 1;
end if;
else
s_next <= s_reg + 1;
end if;
end if;
when stop =>
if (s_tick = '1') then
if s_reg = (SB_TICK - 1) then
state_next <= idle;
rx_done_tick <= '1';
else
s_next <= s_reg + 1;
end if;
end if;
end case;
end process;
dout <= b_reg;
end Behavioral;
/7 
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