通过另一个FSM多次启动FSM

@ macellan85坦率地说，我不明白为什么你不能在RTL中编码和调试它，如果你可以输入你想要的。
这里没有挑战;
只需在描述时对FSM进行编码，然后在模拟器下运行它们，看看你错过了什么。
你在模拟你的设计，是吗？
如果你在通过综合后把它放在硬件上，你应该得到你得到的东西;-)
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。



以下为原文

@macellan85 to be frank, I don't see why you can't code and debug this in RTL if you can type what you want. There is no challenge here; just code the FSMs as you describe and run them under the simulator to see what you missed. You are simulating your design,  yes? If you are putting it on hardware after it passes synthesis, you deserve what you get ;-)
 
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

谢谢@ muzafferfor答案。
其实我没有使用模拟器。
我在开始进行FPGA设计的最初几天尝试过。
然后我很难宣布时钟，现在直接检查范围上的输出。
我也想这样做但是现在我可以用这种方式做一些基本的东西。
如果您有任何有用的文档。
等让我更容易理解模拟问题请告诉我。
另一方面，我不知道为什么它不起作用:)因为它不是那么复杂。
我想我会错过一些东西，另一只眼睛可以识别这个，希望如此。
我附上了vhd设计。
正如我之前所说，它们连接到其他一些模块。
这个过程的一点细节：
flag0 = 1启动FSM1
FSM1产生flag1 = 1，其开始另一个过程以产生确定宽度脉冲（P）以启动FSM2。
在flag2之前P = 0并且重置flag1 = 0。
FSM2在操作期间生成flag2 = 1。
最后它回到flag2 = 0
flag2 = 0将FSM1 ST1的状态改变为ST2，flag1 = 1，并且FSM2再次通过P.
flag2 = 0再次
FSM1返回ST0 flag1 = 0
提前致谢
FSM1.vhd 4 KB
FSM2.vhd 5 KB



以下为原文

 
Thank you @muzaffer for the answer.
 
Actually I'm not using the simulator. I tried it during the first days when I started to do FPGA design. Then I had difficulty to declare the clock and now directly checking the output on a scope. I want to do it as well but for now I can do some basic stuff this way. If you have any useful doc. etc makes understanding the simulation issues little bit easier please let me know.
 
On the other hand, I don't know either why it doesn't work :) since it is not that much complicated. I think I miss something and another eye can identify this, hopefully.
 
I attached the vhd designs. They are connected to some other modules as I said before. Little bit detail of the process:
flag0 = 1 starts FSM1
FSM1 generates flag1 = 1 which starts another process to generate a definite width pulse (P) to start FSM2. P=0 much before flag2 and resets flag1=0.
 
FSM2 generates  flag2 =1 during operation. In the end it goes back to flag2=0
flag2=0 change state of FSM1 ST1 to ST2 , flag1=1, and FSM2 process again through P.
flag2=0 again
FSM1 goes back to ST0 flag1=0
 
Thanks in advance
            FSM1.vhd ‏4 KB                FSM2.vhd ‏5 KB

@macellan85我会指出你这个惊人的新发明，称为互联网和搜索引擎：
https://www.google.com/search?q=how+to+write+a+testbench+in+vhdl
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。



以下为原文

@macellan85 I'd point you to this amazing new invention called the Internet and search engines:
 
https://www.google.com/search?q=how+to+write+a+testbench+in+vhdl
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

感谢您介绍这个惊人的发明@ muzaffer但我需要建议解决我上面的问题:)
我没有观察测试台窗口上的信号，而是可以看到真实的输出。
他们只是不表现我想要他们！
问题：可能是什么问题？



以下为原文

 
Thank you for introducing this amazing invention @muzaffer but I need advice to solve my question above :)  
 
Instead of observing the signals on the test bench window, I can see the real outputs. They just don't behave how I want them !
 
 
Question: What can be the problem?

男，
冒着让你不快乐的风险（你似乎是这样），我只能提出一些建议。
一：你选择的架构很奇怪。
无论您认为它是一个好的解决方案，具有所需状态的简单状态机是更好的方法。
二：当它不起作用时，你需要调试它。
我建议创建一个测试平台，并模拟它以找到你的bug。
最后，虽然我也很想对你这样的问题提供讽刺性的答案，但作为Xilinx的员工，我必须提醒自己，你是客户，按照定义“总是正确的”。
即使是新学生以某种小的方式购买Digilent董事会也能支付我的工资。
谢谢。
将@muzaffer的回复标记为“滥用”确实引起了我的注意。
但是，我会对他太过刻苦，因为他在论坛上回答了很多问题，并且是最重要的回应者之一。
而且，互联网是一个很好的资源。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

m,
 
At the risk of causing you to be unhappy (which it seems you are), I can only make a couple of suggestions.
 
One:  the architecture you have chosen is odd.  Regardless of how you think it is a good solution, a simple state machine with as many states as required is a better approach.
 
Two:  when it doesn't work, you need to debug it.  I suggest creating a testbench, and simulating it to find your bug.
 
Lastly, although I am also tempted to provide a sarcastic answer to questions such as yours, I as a Xilinx employee must remind myself you are the customer, and by definition "are always right."  Even a new student buying a Digilent board in some small way pays my salary.  Thank you.
 
Marking @muzaffer 's reply as 'abuse' did get my attention.  But, I would be too hard on him, as he answers many questions in the forums and is one of the top responders.  And, the internet is a great resource.
Austin Lesea
Principal Engineer
Xilinx San Jose

两个FSM以相同的频率或不同的频率运行吗？
我对FSM1中的状态感到有点困惑：
当ST_FIRST_PART => s_DO_Data_Part s_DO_Set_flag if（s_DO_Period_Flag ='0'）AND（s_DO_Data_Sent_progress_flag ='0'）则NEXT_STATE else s_DO_Set_flag NEXT_STATE结束if;
我看到你试图断言s_DO_Set_flag，但如果if语句计算为FALSE，则s_DO_Set_flag将在同一个时钟周期内置为无效。
也就是说，分配将被覆盖。
因此，如果在FSM进入ST_FIRST_PART状态时不存在评估if语句TRUE所需的条件，则s_DO_Set_flag将永远不会断言。
在转换到ST_FIRST_PART状态时，最好将s_DO_Set_flag断言置于ST_IDLE状态。
其他一些指示：
不要一起使用ieee.std_logic_unsigned和ieee.numeric_std。
只需使用ieee.numeric_std即可。
完全同步的进程只需要灵敏度列表上的时钟。
你必须学会​​模拟。
你会节省很多时间和调试痛苦。
您已经看到，通过自己的承认，调试需要多长时间，而不是复杂的设计。
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

Do the two FSMs run at the same frequency or different frequencies?
 
I'm a bit confused by this state in FSM1:
 
when ST_FIRST_PART =>                    
  s_DO_Data_Part  <= "01110111"; 
  s_DO_Set_flag   <= '1' ;                   
  if ( s_DO_Period_Flag = '0' ) AND ( s_DO_Data_Sent_progress_flag = '0' ) then 
    NEXT_STATE <= ST_SECOND_PART ;
  else
    s_DO_Set_flag   <= '0' ;
    NEXT_STATE      <= ST_FIRST_PART ; 
  end if ;
 
I see you are trying to assert s_DO_Set_flag but if the if statement evaluates FALSE then s_DO_Set_flag will deassert in the same clock cycle. That is, the assignment will be overridden. So, if the conditions required to evaluate the if statement TRUE are not present as the FSM enters the ST_FIRST_PART state, then s_DO_Set_flag will never assert.
 
It would be better to put the s_DO_Set_flag assertion in the ST_IDLE state as you transition to the ST_FIRST_PART state.
 
Some other pointers:
 
Don't use ieee.std_logic_unsigned and ieee.numeric_std together. Just use ieee.numeric_std.
Fully synchronous processes only need the clock on the sensitivity list.
You positively must learn to simulate. You will save yourself so much time and debug pain. You've already seen how long it takes to debug, by your own admission, not a complicated design.
----------
"That which we must learn to do, we learn by doing." - Aristotle

我想我现在会回复自己，我发现有什么事情要好一点。
FSM1使用ST_FIRST_PART作为等待状态，直到发生其他事件，对吗？
如果这是真的，那么忽略我写的东西，因为它根本不正确。
回到我的绘图板！
第一个问题仍然有效 - 两个FSM是由一个公共时钟计时吗？
----------“我们必须学会做的事情，我们从实践中学习。”
- 亚里士多德



以下为原文

i think I shall reply to myself now that I see what is trying to happen a little better.
 
The FSM1 is using the ST_FIRST_PART as a wait state until some other event happens, right? If this is true then ignore what i wrote as it isn't correct at all.
 
Back to the drawing board for me!
 
The first question is still valid though - are the two FSMs being clocked by a common clock?
----------
"That which we must learn to do, we learn by doing." - Aristotle