时钟流混乱

你好@timurgepard，
我的问题是，流程将在一个clokc循环中完成吗？
- >否，您的“A”输入将在第3个时钟沿之后反映在“B”输出。
第一个时钟沿：输入数据D0将反映在X的“X”输出处或者您可以在“Y”的输入处说出
第二个时钟沿：新数据D1将被“X”锁存并将在X的输出处反映。同时Y也将反映Y的输出处的先前数据，即D0。
第3个时钟沿：新数据D2将被“X”锁存并将在X的输出处反映。同时Y也将反映Y的输出处的先前数据，即D1和Z将锁存第1个输入数据D0
并反映在“B”。
希望我的解释清楚。
谢谢，
佳日



以下为原文

Hello @timurgepard ,
 
My question is, will process be finished in one clokc cycle?
--> No, your "A" input will be reflected at "B" output after 3rd clock edge.
 
1st clock edge : Input data D0 will be reflected at "X" output of X Or you can say at the input of "Y"
2nd clock edge : New data D1 will be latched by "X" and will be reflect at the output of X. At the same time Y will also                                       reflect previous data at output of Y that is D0.
3rd clock edge: New data D2 will be latched by "X" and will be reflect at the output of X. At the same time Y will also                                       reflect previous data at output of Y that is D1 and Z will latched the 1st input data D0 and reflected at the                               "B".
 
Hope my explanation is clear.
 
Thanks,
Yash
 

嗨，
图片显示的内容可以描述为流水线设计。
消除时钟将导致大量的组合逻辑。
这消除了延迟，但会产生一些大的延迟。
此外，输出很可能会有毛刺。
更不用说有反馈路径时会发生什么。
在任何情况下，在应用新输入之前，必须等待整个延迟才能获得稳定的输出。
但在流水线设计中，您可以在每个时钟周期输入新数据。
因此，在初始延迟之后，您还会在每个时钟周期获得新结果，然后比纯组合设计快得多。
您现在看到流水线设计如何提高性能？
有一个很好的综合 
Eilert



以下为原文

Hi,
what the picture shows can be described as a pipelined design.
 
Eliminating the clock would result in a big blob of combinatorical logic.
This eliminates the latency but creates some large delay.
Also, the output will most probably have glitches.
Not to mention what might happen when there are feedback paths.
 
In any case, you have to wait for the whole delay to get a stable output before you apply new input.
But in a pipelined design you can feed in new data at every clock cycle.
So after an initial latency you also get new results at each clock cycle, which then is much faster than the pure combinatorcal design.
 
Do you see now how a pipelined design is able to improve performance?
 
Have a nice synthesis
  Eilert

我实际上在内存中回忆起管道。
但是，如果我首先需要测试结果，而不是性能，我可以说像1毫秒的巨大延迟一样，并且当多米诺骰子相互影响时做一切。



以下为原文

I actually recalling pipeline now in memory.
 
But if I need to test results at first, not performance, can I put like HUGE delay say 1 ms, and do everything like when domino dices are affecting each other.
 
 

我的实体中有反馈（inout）。
所以，我认为你们是对的，最好用时钟控制一切。



以下为原文

I have feedback (inout) in my entities.
 
So, I think you right guys, It is better to do with clock controlling everything.

嗨，
除了反馈基本上......是的......但是！
你为什么要在不需要的情况下改变设计？
测试平台可以等待一些时钟周期，然后您就可以获得真实的结果。
因此，最好在您的测试平台上投入一些精力，而不是搞乱您的设计资源。
有一个很好的模拟 
Eilert



以下为原文

Hi,
apart from the feedback basically... yes... BUT!
Why do you want to change the design, without need?
A testbench can wait for some clock cycles, and then you have the real result.
So better put some effort into your testbench than messing around with your design sources.
 
Have a nice simulation
  Eilert

原因主要在于我之前使用LUT生成正弦波的线程。
根据我为正弦波发生器设计的设计，它在每3个时钟周期产生输出。
但总体设计并非简单的正弦波发生器，它是锁相环，它根据输入和内部方波发生器（DDS）相位差产生频率分量。
幸运的是，输入不是正弦波，它也是squre wave，1或0。
所以我看看它是输入的1/0还是DDS的1/0。
如果它类似于输入中的顺序1,0,1,0，则来自DDS的1。
我需要添加以增加DDS的频率成分。
只有这样，在我从DDS获得稳定的频率后，我需要将它提供给正弦波发生器。
但是你说我可以使用LUT操纵正弦波频率。
但在此之前，我必须对这3个clokc周期做一些事情。
或者可能会改变输入频率。
你看，这是一项复杂的任务



以下为原文

The reason basically lies with my previous thread of  sine wave generation with LUT.
 
Based on design I made for sine wave generator , it produces output in each 3 clock cycles. 
 
 
But overall design is not simple sine wave generator, it is Phase Locked Loop, which generates frequency component based on input and Internal Square wave generator (DDS) phase difference.
 
Fortunately, input is not sine wave, it is also squre wave,  1 or 0.
 
So I look if it is 1/0 from Input or 1/0 from DDS. If it is like sequentional 1, 0 , 1, 0 from Input and then 1 from DDS. I need to  add  to increase frequency component of DDS. 
 
Only then, after I have stable frequency from DDS, I need to supply it to sine wave generator. But you said that I can manipulate sine wave frequency using LUT. But before that, I had to do something with this 3 clokc cycles. Or may be change input frequency. You see  it's quite complicated task

实际上是减法，因为用Phase操纵是明智的。



以下为原文

Actually substract, since it is sensible to manipulate with Phase.

eilert，可能会理解。
我找到了频率到相位转换的公式和种类，但是无法得到它。
如果你以前见过它，可能你有一些知识吗？
fout = fclock *（每个完整周期a /＃步）* 2 ^ 16 * fin
fout / fin = fclock *（每个完整周期a /＃步）* 2 ^ 16
a =每个完整周期#step /（fclock * 2 ^ 16）
让#step每个完整周期= 2 ^ 60（60位长信号）来克服时钟频率100MHz。= 10 ^ 8
a = 2 ^ 60 /（10 ^ 8 * 2 ^ 16）= 175922。
阶段步骤= a * fin。
阶段=阶段+阶段。
1.为什么2 ^ 16？
2究竟什么是“a”？
HowPhase步骤变成了* fin。
我知道LUT中的THETA增量应该是= + 1
但是通过取（49到40）位的相位（长度减少到2 ^ 50），他们以某种方式实现了这一点。
我觉得我的大脑会爆炸



以下为原文

eilert, may be could understand. I found formula and kind of deriviation of frequency to phase convertion, but couldnt get it. IF you ever saw it before, may be you have some knowledge?
 
 
fout = fclock * (a/ # step per full cycle) * 2^16 * fin
 
fout/ fin =  fclock * (a/ # step per full cycle) * 2^16
 
a = #step per full cycle/ (fclock * 2^16)
 
 Let's #step per full cycle  = 2^60 (60 bit length signal) to overcome clock frequency 100MHz.=10^8
 
a= 2^60 / ( 10^8 * 2^16) = 175922. 
 
Phase step = a * fin.
 
Phase = Phase + Phase step.
 
1. Why 2^16?
2 What is "a" exactly? How Phase step becomes  a * fin.
 
I know that THETA increment in LUT should be =+1
 
 
But by taking (49 to 40) bits of Phase (with length reduced to 2^50) they somehow achieve that.
 
My brain can explode I feel

嗨，
您找到的公式只是将输入频率分成几个时钟周期，然后它可以与指导时钟同步。
这就是PLL的作用。
通过添加一些分频器，它还可以将输入频率相乘以产生更高的输出频率。
但这是一些复杂的控制电路。
猜猜为什么FPGA有DCM和PLL可用作硬连线元件。
我怀疑你只是在考虑过于复杂。
有一个矩形并推动它通过一些PLL来获得另一个矩形几乎不会让你更接近生成一个正弦波。
DDS块可以直接执行此操作。
但是如果你想要一些代码来咀嚼，这里是一个生成没有波表的正弦波的代码示例：
http://forums.xilinx.com/t5/General-Technical-Discussion/Generating-SIne-Wave/m-p/53201#M2551
在同一个帖子中，你之前的一些帖子也找到了理论背景的链接，并使搜索更简单，它也被我发布了。
:-)
有一个很好的综合 
Eilert



以下为原文

Hi,
the formula you found just divides the input frequency into a fraction of clock cycles and then it can be synchronized to the guiding clock. That's what a PLL does. With some frequency divider added it can also multiply the incoming frequency to generate a higher output frequency.
 
But that is some complicated control circuit. Guess why FPGAs have DCMs and PLLs available as hardwired elements.
I suspect that you are just thinking overly complicated.
Having a Rectangle and pushing it through some PLL to get another rectangle barely gets you anyhow closer to generate a sinewave.
 
The DDS block can do this directly.
But if you want some code to chew on, here's an example of code that generates a sine wave without a wavetable:
 
http://forums.xilinx.com/t5/General-Technical-Discussion/Generating-SIne-Wave/m-p/53201#M2551
 
In the same thread, some posts before you also find a link to the theoretical background, and to make the search simpler, It has been posted by me too. :-)
 
Have a nice synthesis
  Eilert