为什么更改define指令值会导致失败？

当设计从运行到运行失败时，如您所描述的那样，根本原因通常是设计中的时间问题。
这要么是缺少本应应用于设计的时序约束，未正确处理的时钟域交叉，要么是未正确处理的同步逻辑的异步输入。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
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以下为原文

When designs fail from run to run with minor changes like you have described the root cause is usually a timing issue in the design.  This is either missing timing constraints that should have been applied to the design, clock domain crossings that are not correctly handled, or asynchronous inputs to synchronous logic that are not correctly handled.
------Have you tried typing your question into Google?  If not you should before posting.
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附件是我用于设计的ucf文件。
在这种情况下如何调试。
我不是这个项目的原始设计师，但我必须调试设计，因为原设计师离开了。
我该怎么调试呢？
谢谢
*论坛管理员删除了附件



以下为原文

The attachment is a ucf file I use for the design. How do I debug in this situation. I am not the original designer of this project, but I have to debug the design since the original designer left. How can I debug this? 
 
Thanks
 
*attachment removed by Forums admin

有没有办法让它稳定或使用一些约束，如KEEP或S属性，使其一致？



以下为原文

Is there any way to make it stable or use some constraint such as KEEP or S property to make it consistant? 

您无法使用KEEP和S约束来解决时序问题。
设计可能正在用于测试的部分，但是一旦你开始在多个部分上尝试这个，你就会开始看到失败。
您需要深入了解设计并找到根本原因。
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

You cannot fix timing issues with KEEP and S constraints.  The design may be working on the part that you are using for testing, but once you start trying this on multiple parts you will start seeing failures.  You need to get in to the design and find the root cause.
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

qizhong19920114写道：
我从`define FCORE_REV_ID 8'h22改为`defineFCORE_REV_ID 8'h24
FCORE_REV_ID只是固件的修订版号，与固件功能无关，但只是由PC设备驱动程序读取，以向用户显示修订版号。
我从22变为24，并且电路板不能正常工作。
可能是造成这个问题的原因是什么？
谢谢
定义“不会按原样运行”。
正如Ed所说，这可能是一个时间问题。
你的时间限制是什么，你在遇到它们吗？
----------------------------是的，我这样做是为了谋生。



以下为原文

qizhong19920114 wrote:
I change from `define FCORE_REV_ID 8'h22 to `define FCORE_REV_ID 8'h24
 
The FCORE_REV_ID is just a revision number for the firmware that does not have anything to do with the firmware function but is just read by the pc device driver to show the user what the revision number is. I changed from 22 to 24 and the board doesn't function the way it was. What could be the cause of this problem? 
 
Thanks

Define "doesn't function the way it was."
 
As Ed says, it's likely a timing issue. What are your timing constraints, and are you meeting them?
----------------------------Yes, I do this for a living.

该系统是一个通信系统。
我从发送器端口到接收器端口进行测试，并检查接收器端的数据，如果系统正常运行，该数据应该与发送器发送的数据相匹配。
在更改定义值之前，接收的数据与发送器数据匹配，但是在定义更改后数据出错并且不匹配。
附件是我使用的时间约束。
当我在PAR报告中检查约束时，我不认为我满足所有这些。
这是正确的检查地点吗？
或者我应该查看TRCE报告？
以下是我用来执行TRCE的命令，但我没有看到报告显示是否满足约束。
我应该在trce命令中使用哪个编译标志？
trce -v 10 sfscc_complete_top_routed.ncd sfscc_complete_top.pcf> trce.txt
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以下为原文

The system is a communication system. I do a test from transmiter port to receiver port, and check the data at the receiver end which should match the data being sent from the transmitter if the system is function correctly. 
 
The received data match the transmiter data before I change the define value but the data goes wrong and mismatch after the define being changed. 
 
The attachment is a timing constraint I use. I don't think I meet all of them when I check the constraint at PAR report. Is this the correct place to check? 
 
Or should I check the TRCE report? The following is the command I use to do TRCE but I didn't see the report showing about constraint met or not. Which compiling flag should I use in trce command?  
trce -v 10 sfscc_complete_top_routed.ncd sfscc_complete_top.pcf > trce.txt
 
*attachment removed by Forums admin
 

par.txt中跳出来的第一件事就是你没有找到你设计的所有针脚！
接下来，你有几个：
警告：路由：455  -  CLK Net：CLK可能有过度偏斜，因为 
0 CLK引脚和4个NON_CLK引脚无法使用CLK模板进行路由。
错误。
无论出于何种原因，似乎您的时钟不在时钟网上，这是未能满足约束的明显原因。
事实上，这些工具似乎认为你有30个时钟！
听起来像编码风格的问题。
----------------------------是的，我这样做是为了谋生。



以下为原文

The first thing in your par.txt that jumps out at me is that you have not located ALL of your design's pins!
 
Next, you have a few:
WARNING:Route:455 - CLK Net:CLK may have excessive skew because       0 CLK pins and 4 NON_CLK pins failed to route using a CLK template.errors.
Seems like your clock isn't on a clock net, for whatever reason, and this is an obvious cause of failures to meet constraints. In fact, the tools seem to think you have something like 30 clocks!
 
Sounds like a coding style problem.
----------------------------Yes, I do this for a living.