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你好,
我使用Virtex7的HP库来实现DDR3控制器。 我的控制器将以1600Mbps的速度运行,因此主控制器中的VRN和VRP应连接一个80Ω电阻,以实现更高的性能。 实现addr / cmd信号的中间存储区是DCI_CASCADE中的主控。 而且在addr / cmd存储区中,我希望使用其余的引脚来传输和接收具有SOSTLARD的IOSTANDARD的单端信号。 80Ω外部电阻适用于SSTL15_T_DCI吗? 谢谢! 以上来自于谷歌翻译 以下为原文 Hello, I use HP banks of Virtex7 to implement DDR3 controller. My controller will operate at 1600Mbps, so the VRN and VRP in the master bank should tie a 80Ω resistor to achieve higher performance. The middle bank which implements the addr/cmd signals is the master in the DCI_CASCADE. And also in the addr/cmd bank, I want using the rest pins to transmmit and receive single end signals with the IOSTANDARD of SSTL15_T_DCI. Does the 80Ω external resistor applicable to SSTL15_T_DCI? Thanks! |
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嗨,
我认为你指的是在中间库中终止你未使用的I / O引脚(DQ / DQS)。 如果它们被用作输入DCI就足够了,如果输出/ bidirectoon然后终止将类似于存储器端的ODT,这由模式寄存器值设置.80欧姆是分离终止的典型值,但是我们强烈建议去IBIS 模拟,然后进行最后的调用 问候, Vanitha -------------------------------------------------- -------------------------------------------请在发布前进行谷歌搜索, 您可能会找到相关信息。请留下帖子 - “接受为解决方案”,如果提供的信息有用且回复,请给予赞誉 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Hi, I think you are referring termination of your uused I/O pins (DQ/DQS) in the middle banks. If they are used as inputs DCI would be sufficient, if outputs /bidirectoon then termination would be similar to ODT at memory end, which is set by mode register values. 80Ohms is typical value for Split Termination, however we strongly recommend to go for IBIS simulations and then take the final call Regards, Vanitha --------------------------------------------------------------------------------------------- Please do google search before posting, you may find relavant information. Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented View solution in original post |
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嗨,
DCI不适用于地址和控制,其IOSTANDRD是SSTL。 80Ω外部电阻不适用于SSTL15_T_DCI 有关地址和控制的信息,请参阅UG586终端导向部分 “地址和控制信号(A,BA,RAS_N,CAS_N,WE_N,CS_N,CKE,ODT)是 使用板载DIMM终端进行终止。 如果DIMM终止没有 存在或正在使用一个组件,在该线路的远端向VTT上拉 应该使用(图1-88)。 除了需要差分的CK / CK_N 终止,如图1-90所示) 编辑: - 所有IOstanadards也不兼容SSTL_T_DCI,请通过UG471 在同一银行中组合I / O标准的规则并采取相应措施 IBIS模拟适当的外部终止值。 希望这可以帮助 问候, Vanitha -------------------------------------------------- -------------------------------------------请在发布前进行谷歌搜索, 您可能会找到相关信息。请留下帖子 - “接受为解决方案”,如果提供的信息有用且回复,请给予赞誉 以上来自于谷歌翻译 以下为原文 Hi, DCI is not applicable for address and control, its IOSTANDRD is SSTL. 80Ω external resistor is not applicable to SSTL15_T_DCI For address and control please refer UG586 termination guideliness section, it says "Address and control signals (A, BA, RAS_N, CAS_N, WE_N, CS_N, CKE, ODT) are to be terminated with the onboard DIMM termination. If DIMM termination does not exist or a component is being used, a 40 pull-up to VTT at the far end of the line should be used (Figure 1-88). Except for the CK/CK_N which requires a differential termination as shown inFigure 1-90) Edit:- Also all IOstanadards are not compatibel with SSTL_T_DCI, please go through UG471 Rules for Combining I/O Standards in the Same Bank and take action accordingly Do IBIS simulations for proper external terminatioon values. Hope this helps Regards, Vanitha --------------------------------------------------------------------------------------------- Please do google search before posting, you may find relavant information. Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented |
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嗨,vsrunga
是的,addr / cmd存储区不使用SSTL15_T_DC,即SSTL15。 在我的设计中,addr / cmd信号'IOSTANDARD是SSTL15,它不是DCI。 我将addr / cmd bank中未使用的引脚的IOSTANDARD设置为SSTL15_T_DCI。 我只需在addr / cmd bank中应用80ΩVRN和VRP,并使用“set_property DCI_CASCADE {34 36} [get_iobanks 35]”将addr / cmd bank设置为master。 我在这里使用了DCI_CASCADE,因此dq / dqs库中的VRN和VRP引脚可以用作常规引脚。 在ug586中,它表示“单端40Ω走线和终端需要以1,333 Mb / s和更高的速度运行”。 据此,我选择80Ω外接电阻。 我认为80Ω可以应用于dq和dqs(IOSTANDARD是SSTL15_T_DCI和DIFF_SSTL15_T_DCI),它应该适用于我自己定义的引脚。 我认为听起来对吗? 以上来自于谷歌翻译 以下为原文 Hi, vsrunga Yes, the addr/cmd bank doesn't use SSTL15_T_DC, which is SSTL15. In my design, the addr/cmd signals' IOSTANDARD are SSTL15, which is not DCI. And I set the IOSTANDARD of unused pins in the addr/cmd bank as SSTL15_T_DCI. I just apply 80Ω VRN and VRP in addr/cmd bank, and use "set_property DCI_CASCADE {34 36} [get_iobanks 35]" to set the addr/cmd bank as master. I used DCI_CASCADE here, so the VRN and VRP pins in the dq/dqs banks could be used as regular pins. In ug586, it says "Single ended 40Ω traces and termination are required for operation at 1,333 Mb/s and higher". According to that, I choose the 80Ω external resistor. I think the 80Ω could be applied to dq and dqs( IOSTANDARD is SSTL15_T_DCI and DIFF_SSTL15_T_DCI), it should be applicable to the pins defined by myself. Does what I think sounds right? |
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嗨,
我认为你指的是在中间库中终止你未使用的I / O引脚(DQ / DQS)。 如果它们被用作输入DCI就足够了,如果输出/ bidirectoon然后终止将类似于存储器端的ODT,这由模式寄存器值设置.80欧姆是分离终止的典型值,但是我们强烈建议去IBIS 模拟,然后进行最后的调用 问候, Vanitha -------------------------------------------------- -------------------------------------------请在发布前进行谷歌搜索, 您可能会找到相关信息。请留下帖子 - “接受为解决方案”,如果提供的信息有用且回复,请给予赞誉 以上来自于谷歌翻译 以下为原文 Hi, I think you are referring termination of your uused I/O pins (DQ/DQS) in the middle banks. If they are used as inputs DCI would be sufficient, if outputs /bidirectoon then termination would be similar to ODT at memory end, which is set by mode register values. 80Ohms is typical value for Split Termination, however we strongly recommend to go for IBIS simulations and then take the final call Regards, Vanitha --------------------------------------------------------------------------------------------- Please do google search before posting, you may find relavant information. Mark the post - "Accept as solution" and give kudos if information provided is helpful and reply oriented |
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