RTL与技术原理图怎么更好地查看

如果您怀疑“连接问题”，如您认为设计的实例和子实例之间可能存在错误连接，那么我将使用RTL原理图。
这两个原理图都将为您提供实例化用户模块的准确表示。
实际上，如果在合成中打开展平，则只有RTL原理图将保留您的层次结构。
在扁平设计中寻找错误的顶层网连接，就像在30,000英尺的客机上观察它时，试图在盘子上跟随单股意大利面。
所以，就像几乎所有事情一样，答案是“它取决于”。
RTL原理图是一个非常有用的工具。
它为您提供了一个相对较高的水平，但仍然是结构性的方式来看待您的设计。
是的，如果您怀疑合成问题（很少见），您需要查看技术视图，但是为了在早期阶段可视化您的设计，RTL视图是完全可以接受的，并且（如上所述），如果您已经扁平化
如果您正在查看不正确的顶级连接，那么您的层次结构是唯一的方法。
Avrum
在原帖中查看解决方案



以下为原文

If you suspect "connectivity issues", as in you think there may be a mis-connection between the instances and sub-instances of your design, then I would use the RTL schematic.
 
Both schematics will give you an accurate representation of your instantiated user modules. In fact, if flattening is turned on in synthesis, then only the RTL schematic will preserve your hierarchy. Looking for an erroneous top level net connection in a flattened design is like trying to follow a single strand of spaghetti on a plate when you are looking at it from an airliner at 30,000 feet.
 
So, like almost all things, the answer it "it depends". The RTL schematic is a very useful tool. It gives you a relatively high level, but yet still structural, way of looking at your design. Yes, if you suspect synthesis problems (which are rare), you need to look at the technology view, but for visualizing your design at the early stages the RTL view is perfectly acceptable, and (as I said above), if you have flattened your hierarchy is the only way to go if you are looking at an incorrect top level connection.
 
Avrum
View solution in original post

您好，是的，如AR＃41500中所述，您应该始终参考技术原理图。
即使对于你的情况（即，解决连接问题），我建议你看一下技术schemactic中信号的连通性。谢谢，VinayThanks，Vinay
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以下为原文

Hello,

Yes, as mentioned in AR#41500, you should always refer to technology schematic.

Even for your case (i.e., troubleshooting connection issues), I suggest you to look at the connectivity of the signals in technology schemactic.

Thanks,
Vinay

Thanks,
Vinay--------------------------------------------------------------------------------------------
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嗨，
技术原理图给出了接近FPGA视图的设计，RTL原理图没有给出。
技术原理图根据FPGA上使用的组件提供信息。
例如BUFFER，LUT。
RTL原理图没有提供这些细节。
它给出了门。
谢谢，AnirudhPS：请将此标记作为答案，以防它有助于解决您的问题。如果帖子引导您找到解决方案，请给予赞誉。



以下为原文

Hi,
 
The technology schematics gives a near to FPGA view of the design which the RTL schematic does not give.
 
The technology schematic, gives the information based on the components used on the FPGA. eg BUFFERs, LUT's. The RTL schematic does not give these details. It gives in terms of gates.
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

如果您怀疑“连接问题”，如您认为设计的实例和子实例之间可能存在错误连接，那么我将使用RTL原理图。
这两个原理图都将为您提供实例化用户模块的准确表示。
实际上，如果在合成中打开展平，则只有RTL原理图将保留您的层次结构。
在扁平设计中寻找错误的顶层网连接，就像在30,000英尺的客机上观察它时，试图在盘子上跟随单股意大利面。
所以，就像几乎所有事情一样，答案是“它取决于”。
RTL原理图是一个非常有用的工具。
它为您提供了一个相对较高的水平，但仍然是结构性的方式来看待您的设计。
是的，如果您怀疑合成问题（很少见），您需要查看技术视图，但是为了在早期阶段可视化您的设计，RTL视图是完全可以接受的，并且（如上所述），如果您已经扁平化
如果您正在查看不正确的顶级连接，那么您的层次结构是唯一的方法。
Avrum



以下为原文

If you suspect "connectivity issues", as in you think there may be a mis-connection between the instances and sub-instances of your design, then I would use the RTL schematic.
 
Both schematics will give you an accurate representation of your instantiated user modules. In fact, if flattening is turned on in synthesis, then only the RTL schematic will preserve your hierarchy. Looking for an erroneous top level net connection in a flattened design is like trying to follow a single strand of spaghetti on a plate when you are looking at it from an airliner at 30,000 feet.
 
So, like almost all things, the answer it "it depends". The RTL schematic is a very useful tool. It gives you a relatively high level, but yet still structural, way of looking at your design. Yes, if you suspect synthesis problems (which are rare), you need to look at the technology view, but for visualizing your design at the early stages the RTL view is perfectly acceptable, and (as I said above), if you have flattened your hierarchy is the only way to go if you are looking at an incorrect top level connection.
 
Avrum