如何在发生冲突时设置全局资源

你好，
请告诉我你想从Time8块中生成什么时间。你想把一个250Hz的时钟输入到Time8块。有几种解决办法：
1。如果UART和Time8块的操作是互斥的：在这种情况下，每当你想使用Time8时，你可以修改VC分频器来产生所需频率的时钟。但是你不能改变SysCLK，所以Time8的时钟应该来源于其他模块，当UART必须被使用时，VC分频器应该被切换回正常模式。请注意，两者不能同时工作。
2。如果两者都应该一起工作，那么你需要另一个块，它应该把VC除法器除以所需的时钟，然后将其发送到Time8块。这取决于你的设备所拥有的数字块的数量。
最好的问候，
普什克



     以下为原文
   Hi,
     
    Please let me know what is the timing which you want to generate from Timer8 block. You want to source a clock of 250Hz to Timer8 block. There are a couple of solutions for this:
     
    1. If operation of UART and Timer8 block is mutually exclusive: In this case, whenever you want to use Timer8, at that time you can modify the VC dividers to generate a clock of required frequency. But you cannot change the SysClk, so clock of Timer8 should be sourced from some other module and when UART has to be used VC dividers should be switched back to the normal mode. Please note that both of them cannot work simultaneously.
    2. If both of them are supposed to work together, then you'll need another block which should divide the VC dividers to a required clock and then source it to Timer8 block. This would depend on the number of digital blocks your device have.
     
    Best regards,
    Pushek

据我所知，你不能改变YSLCK，你只能改变CPUK的分频器。
如果你想为你的Time8生成一个250Hz的时钟，你不能那样做。你可以从VC3得到的最低值是366Hz。你要么使用两个定时器，一个16位定时器，要么在一个中断中做一些除法，并敲击定时器应该输出的任何输出。
好消息是叶子VC3可用于UART。：）



     以下为原文
  As far as I know you can't change SYSCLK, you can only change CPU_CLK's divider.
    If you're trying to generate a 250Hz clock for your timer8 you can't do it that way. The lowest value you can get from VC3 is 366Hz. You're either going to have to use two timers, a 16-bit timer or do some division in an interrupt and bit-bang whatever output the timer is supposed to drive.
    The good news is that leaves VC3 available for the UART. :)