是CE还是重置/SET？

newhunt163写道：
你好： 
显然，第二种方式会导致CE控制和CE =（非A）和B，其中不能有复位/设置控制。与第一种方法相比，第二种方法没有复位/设置，但使用了
逻辑功能。
当然，逻辑功能“和”应该由LUT完成。 
现在我的问题是我想使用更小的资源和更高的速度。
但第一种方式将使用reset / set，尽管没有逻辑延迟。
然而，第二种方式将使用LUT并再次使用逻辑延迟。 
那么应该推荐哪种方式？ 
您能比较资源利用率和速度平台Virtex-6或Spatan-6的两种方式吗？
您可能会对合成器对任何特定逻辑描述的作用感到惊讶。
请记住，在每个触发器的D输入前面是一个四或五或六输入LUT（以及一些多路复用器），它们可以实现相当复杂的逻辑，而不仅仅是简单的AND门。
它可以在不使用触发器的CE或同步设置/复位输入的情况下计算出所需的逻辑。
或者它可能会以您不期望的方式分解逻辑。
另外，不要忘记设置/重置输入不必来自全局资源;
它可以来自驱动它的逻辑，它可能很好地处于相同的切片中。
你应该做的是写一些代码，启动XST，看看它做了什么。
在设计时，编写人类读者可以很好理解的代码，并且只有在未能满足时序或资源耗尽时才关注这种详细的优化。
在绝大多数情况下，两者都不是问题。
----------------------------是的，我这样做是为了谋生。



以下为原文

newhunt163 wrote:
Hello:      
       Obviously, the second way will lead to a CE contorl and CE= (not A) and B, where can't have a reset/set control.Comparing with the first method, the second one have no reset/set , but use a logic function. Of course, the logic function "and" should be completed by a LUT.     
       Now My question is I want to use smaller resource and higher speed. But the first way will use reset/set ,although no  logic delay. However the second way will use a LUT and again a logic delay.    
        So which way should be recommended?     
        Can you compare the two ways in resource utilization and in speed taking platform Virtex-6 or Spatan-6?   
 

You might be surprised by what the synthesizer does with any particular logic description. Remember that in front of each flop's D input is a four- or five- or six-input LUT (as well as some muxes), which can implement fairly complex logic, more than just simple AND gates. It may very well be able to work out the desired logic without using either the flop's CE or the sync set/reset inputs. Or it might split up the logic in ways you don't expect.
 
Also don't forget that the set/reset input doesn't have to come from a global-ish resource; it can come from the logic that drives it, which may very well be in the same slice.
 
What you should do is write some code, fire up XST, and see what it does.
 
And when designing, write code that the human reader can understand well, and be concerned with this sort of detailed optimization only if you fail to meet timing or you run out of resources. In the vast majority of cases, neither will be an issue.
----------------------------Yes, I do this for a living.

ddemmin写道：
我不认为那些白皮书会让你无法使用设置/重置功能。
他们说不要在不需要的地方使用重置/设置，逻辑将出现在已知状态。
建议不使用全局重置，因为配置确实确保逻辑在已知状态下出现。
显然，逻辑块可能需要本地复位，具体取决于设计要求。
我认为这里的真正建议是：“不要过度思考它！”
----------------------------是的，我这样做是为了谋生。



以下为原文

ddemmin wrote:
 
I do not think those white papers are discouraging you from using set/reset functionalily.  They are saying dont use reset/set where it is not needed, the logic will come up in a known state.

The recommendation is to not use a global reset, because the configuration does indeed ensure the logic comes up in a known state. Obviously, logic blocks may need a local reset, depending on the design requirements. 
 
I think the real advice here is: "don't overthink it!"
----------------------------Yes, I do this for a living.

两个块的行为不一样。
在一种情况下，输出为零（第一），在另一种情况下，输出记住其先前值（第二）。
很难比较表现不同的事物的实现。
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。



以下为原文

The behavior of the two blocks is not same. In one case there is a zero assignment to output (first), in the other case output remembers its previous value (second). It's difficult to compare implementation of things which behave differently.- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

首先，感谢您对我的问题的回复。
其次，我很抱歉我的错误，功能表与我的VHDL代码不同。
第三，我必须用一个更简单的例子来解释我的问题。 
通常，如果有一个控件使“output ='0'这样重置/设置conrtol，那么可以转换为逻辑控件。举例：
过程（CLK）
开始 
if（rising_edge（clk）然后 
if（A ='1'）然后 
输出页128：第7章：触发器和寄存器控制信号：，本指南是“尽可能完全避免操作设置/复位逻辑。”。
sowhich推荐的代码风格？
为什么？
2）如果我们将两种代码样式映射到真实硬件，例如Virtex-6，则根据第12页：存储元件 - 控制信号时钟（CLK），时钟使能（CE）和设置
/ reset（SR）对于一个片中的所有存储元素是通用的。 
因此，如果FF已经使用了复位/设置或CE，那么对于Virtex-6，不能使用相同切片中的剩余七个FF，但是四个LUT仍然有机会被使用，这在地图中是正确的
？



以下为原文

 First, thank you for the reply to my question.
Secondly, I am sorry for my mistake that function table is different from my VHDL code.
Thirdly, I must use a simpler example to expalin my question.
          Usually, if there is a control making "output = '0' such reset/set conrtol ,then that can be often tranformed into the logic control.Taking example:
process(clk)
begin
      if( rising_edge(clk) then
         if ( A= '1') then
            output <= '0';
         else
            output <= B;
         end if;
     end if;
end process;
 
      On the basis of my understaning to ISE synthesize,the VHDL code will be synthesized to a FF with reset and the input to the FF is B; So in this way We can realize function Only using one FF.
 
     But if we transform the reset control into the logic control , We can write it to the second way:
process(clk)
begin
      if( rising_edge(clk) then
        output <= ( A= '0') and B;
     end if;
end process;
 
     In this VHDL code, ISE will  synthesize it to : use LUT to realize the logic function (A='0') and B, after the LUT's output is the FF without reset/set. So the second way will use a  LUT and a FF.
     Comparing with the first code, the different is the first one use only one FF,but the FF has a reset/set, However, the second way is to use a LUT and a FF without reset/set.
      So my question is
1) according to the >Page 128: Chapter 7:Flip-Flops and Registers Control Signals:,this guideline is " Whenever possible, avoid operational set/reset logic altogether.".
so which  are code styles recommended? Why?
 
2)  If We map the two code styles into the real hardware , for example Virtex-6,, according to the Page 12: Storage Elements-----The control signals clock (CLK), clock enable (CE), and set/reset (SR) are common to all storage elements in one slice.
     So if a FF has been used a reset/set or CE, then for Virtex-6, the remaining seven FF in the same slice cann't be used,but the four LUT still have chance to be used , This is right in map?

newhunt163写道：
1）根据>第128页：第7章：触发器和寄存器控制信号：，本指南是“尽可能完全避免操作设置/复位逻辑”。
sowhich推荐的代码风格？
为什么？
为什么？
我认为，因为指南涉及绝对最大可能性能，这忽略了大多数时序约束不会将设计推向器件限制的现实。
本文档的第14.1版已经软化了“尽可能避免操作设置/重置逻辑”的指导原则。
2）如果我们将两种代码样式映射到真实硬件，例如Virtex-6，则根据第12页：存储元件 - 控制信号时钟（CLK），时钟使能（CE）和设置
/ reset（SR）对于一个片中的所有存储元素是通用的。 
因此，如果FF已经使用了复位/设置或CE，那么对于Virtex-6，不能使用相同切片中的剩余七个FF，但是四个LUT仍然有机会被使用，这在地图中是正确的
？
我正在研究S6 SLICEL和SLICEM图，实际上，触发器的CE和SR输入很常见。
这意味着如果切片中需要使用CE和/或SR的任何触发器必须具有相同的CE / SR要求。
（片中所有触发器的时钟和时钟极性也必须相同。）切片中的某些触发器当然可以不使用CE输入，而其他触发器也可以。
还要注意CE和SR信号是切片的输入，这意味着用于导出它们的任何逻辑必然来自另一个切片;
没有任何方法可以将切片的LUT用于CE，同时也将这些LUT用于触发器的D输入。
因此，我认为，对于从给定设备中挤出最后一点性能和资源使用的这种程度的担忧被夸大了。
你不应该迷失在这种精细细节的杂草中。
编写代码，使其在功能上正确且易于人类读者/维护者理解。
绝大多数设计不必“尽可能快地”运行，他们只需要满足时机要求。
仅在未能关闭计时或路由/区域问题时才进行优化。
----------------------------是的，我这样做是为了谋生。



以下为原文

newhunt163 wrote:
 
1) according to the >Page 128: Chapter 7:Flip-Flops and Registers Control Signals:,this guideline is " Whenever possible, avoid operational set/reset logic altogether.".
so which  are code styles recommended? Why?
 
Why? I think because that the guidelines are concerned with absolute maximum possible performance, which ignores the reality that most timing constraints are not pushing the designs to the device limits.
 
Version 14.1 of this document has softened that guideline to "Avoid operational set/reset logic whenever possible."
 
2)  If We map the two code styles into the real hardware , for example Virtex-6,, according to the Page 12: Storage Elements-----The control signals clock (CLK), clock enable (CE), and set/reset (SR) are common to all storage elements in one slice.
     So if a FF has been used a reset/set or CE, then for Virtex-6, the remaining seven FF in the same slice cann't be used,but the four LUT still have chance to be used , This is right in map?

I'm looking at the S6 SLICEL and SLICEM diagram, and indeed, the flops' CE and SR inputs are common. What this means is that if any flops in the slice which need to use CE and/or SR must have the same CE/SR requirements. (The clock, and the clock polarity, for all flops in the slice must be the same, too.) It is certainly possible for some of the flops in the slice to not use the CE input while others do. 
 
Also note that the CE and SR signals are inputs to the slice, which means that necessarily any logic used to derive them must come from another slice; there isn't any way to use the slice's LUTs for the CE while also using those LUTs for the D inputs to the flops.
 
So, again, I think that these level of concern about wringing the last bit of performance and resource usage out of a given device is overblown. You shouldn't get lost in the weeds of this fine-level of detail. Write your code so that it's functionally correct and easy for the human reader/maintainer to understand. The vast majority of designs don't have to run "as fast as possible," they just need to meet timing. Optimize only if you fail to close timing or if you have routing/area issues. 
----------------------------Yes, I do this for a living.