输入抖动与收紧周期约束有什么不同？

埃里克
是的
在每条路径上评估抖动，并要求您输入时钟抖动和系统抖动。
35ps P-P是大多数晶体振荡器提供的，100ps至1000ps是合理的系统抖动数。
2.示波器不足以测量峰峰值抖动，除非它有一个抖动测量分析包作为其功能的一部分（今天的高端示波器）。
如果你从未这样做过，也不知道从哪里开始，我建议你去做（很多）关于信号完整性和抖动的阅读。
绕过，去耦，传输线，匹配，或许可能是麦克斯韦方程式的进修课程（并非真正需要，但它完全是关于场和波）。
我在上一篇文章中提出了这个方法。
你似乎错过了一个好的P-P抖动测量设备。
也许你可以租一个。
LeCroy，安捷伦和其他公司都做了一些非常好的产品。
正确设置设备在某种程度上是一门艺术，所以您可以要求销售人员告诉您该设备是如何完成的。
他们还有一些很好的应用笔记。
Austin Lesea主要工程师Xilinx San Jose
在原帖中查看解决方案



以下为原文

Erik,
 
1.  Yes.  The jitter is evaluated on every path, and requires that you enter a clock jitter, and a system jitter.  35ps P-P is what most crystals oscillators deliver, and 100ps to 1000ps is a reasonable system jitter number.
 
2.  An oscilloscope is insufficient to measure peak to peak jitter, unless it has a jitter measurement analysis package as part of its function (high end scopes do today).  If you have never done this, and do not know where to start, I suggest you go do (a lot) of reading on signal integrity, and jitter.  Bypassing, decoupling, transmission lines, matching, and perhaps a refresher course for Maxwell's equations (not really required, but it is all about fields, and waves).
 
I suggested the method in my last post.  You seem to missing a good P-P jitter measurement device.  Perhaps you can go rent one.  LeCroy, Agilent, and others make some very good ones.  Setting up the equipment properly is somewhat of an art, so you may request the salesman for that equipment show you how its done.  They also have some good applications notes.
 
Austin Lesea
Principal Engineer
Xilinx San JoseView solution in original post

埃里克，
没有。
如果你知道你在做什么。
通过工具自动从最小周期中减去总峰值到峰值抖动的一半，因此您不必自己完成此操作。
您必须输入时钟源抖动和系统抖动（由PCB布局创建的抖动，绕过解决方案，IO切换等），而时钟抖动（MMCM，PLL，DCM）抖动全部由工具计算
并加起来。
如果您不知道系统抖动，请从100 ps峰峰值开始。
在非常激进的设计中，旁路不良或大量IO强烈切换，它可能高达1000 ps，甚至更高。
您可以通过使用DDR IOB DFF在IO引脚上输出有问题的时钟来测量系统抖动，以便可以在外部进行测量。
偶尔的数据错误或逻辑错误通常是由于没有考虑抖动和时间不足而引起的。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Eric,

None.  If you know what you are doing.
 
One half the total peak to peak jitter is automatically subtracted from the minimum period by the tools, so you don't have to do this yourself.
 
You do have to enter the clock source jitter, and the system jitter (jitter created by your pcb layout, bypassing solution, IOs switching, etc.), while the clock jitter (MMCM, PLL, DCM) jitter is all calculated by the tools and added up.
 
If you don't know your system jitter, start with 100 ps peak to peak.  In a very aggressive design, with poor bypassing, or lots of IOs strongly switching, it can be as much as 1000 ps, or even more.  You can measure your system jitter by bringing the clock in question out on an IO pin useing the DDR IOB DFF, so that it may be measured externally.
 
Occasional data errors, or logic errors, are often caused by not taking jitter into account, and having insufficient slack in your timing.
Austin Lesea
Principal Engineer
Xilinx San Jose

谢谢你的回答，我有两个跟进问题：
1）我是否理解您正确的工具将通过设计转发我的抖动约束（DCM等）（我正在运行ISE 11.4）？
我可以确认抖动是以某种方式转发的吗？
看看我对时钟不确定性的时序报告，我看到了我的输入抖动（我还没有对时钟约束添加任何其他不确定性）但是我没有看到添加了DCM的任何抖动？
它是否正确？
我附上了跟踪报告文件以供参考。
2）我想在你消化时保证系统抖动。
您是否有任何参考“逐步指导测量您的系统抖动傻瓜”？
除了示波器之外，我还需要其他任何测量设备吗？
谢谢
/埃里克
fpga_top_xc3s1600e.twx 806 KB



以下为原文

Thanks for the answer, I have two follow up questions:
 
1) Do I understand you correct that the tools will forward my jitter constraint through the design (DCMs etc) (I am running ISE 11.4)? Can I confirm that the jitter is forwarded some way? Looking at my timing report for the Clock Uncertainty I see my input jitter (I have not added any other uncertanty to the clock constraint yet) but I don't see any jitter from the DCM added? Is this correct? I have attached my trace report file for reference.
 
2) I would like to meassure the system jitter as you sugest. Do you have any refernce to a "measure your system jitter for dummies" step by step guide? Do I need any other measuring equipment other then a oscilloscope?
 
Thanks
/Erik
            fpga_top_xc3s1600e.twx ‏806 KB

埃里克
是的
在每条路径上评估抖动，并要求您输入时钟抖动和系统抖动。
35ps P-P是大多数晶体振荡器提供的，100ps至1000ps是合理的系统抖动数。
2.示波器不足以测量峰峰值抖动，除非它有一个抖动测量分析包作为其功能的一部分（今天的高端示波器）。
如果你从未这样做过，也不知道从哪里开始，我建议你去做（很多）关于信号完整性和抖动的阅读。
绕过，去耦，传输线，匹配，或许可能是麦克斯韦方程式的进修课程（并非真正需要，但它完全是关于场和波）。
我在上一篇文章中提出了这个方法。
你似乎错过了一个好的P-P抖动测量设备。
也许你可以租一个。
LeCroy，安捷伦和其他公司都做了一些非常好的产品。
正确设置设备在某种程度上是一门艺术，所以您可以要求销售人员告诉您该设备是如何完成的。
他们还有一些很好的应用笔记。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Erik,
 
1.  Yes.  The jitter is evaluated on every path, and requires that you enter a clock jitter, and a system jitter.  35ps P-P is what most crystals oscillators deliver, and 100ps to 1000ps is a reasonable system jitter number.
 
2.  An oscilloscope is insufficient to measure peak to peak jitter, unless it has a jitter measurement analysis package as part of its function (high end scopes do today).  If you have never done this, and do not know where to start, I suggest you go do (a lot) of reading on signal integrity, and jitter.  Bypassing, decoupling, transmission lines, matching, and perhaps a refresher course for Maxwell's equations (not really required, but it is all about fields, and waves).
 
I suggested the method in my last post.  You seem to missing a good P-P jitter measurement device.  Perhaps you can go rent one.  LeCroy, Agilent, and others make some very good ones.  Setting up the equipment properly is somewhat of an art, so you may request the salesman for that equipment show you how its done.  They also have some good applications notes.
 
Austin Lesea
Principal Engineer
Xilinx San Jose

不需要爱因斯坦的狭义相对论吗？谢谢！



以下为原文

No need for Einstein's special theory of relativity?

Thanks!

埃里克
不。如果您正在设计GPS系统，那么这很有用。
抖动是高速数字设计中最模糊的问题之一，尤其是串行链路（多千兆位收发器），所以它绝对是值得了解的。
如果您确实成为该领域的专家，您将成为为数不多的人之一。
一个好的起点是阅读Howard Johnson的书籍，如“高速数字设计，黑魔法手册”。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Erik,

No.  Although that is useful if you are designing a GPS system.
 
Jitter is one of the most obscure issues with high speed digital design, and especially with serial links (multi-gigabit transceivers), so it is definitely something that is good to know.  If you do become an expert in the field, you will be one of the very few.
 
A good place to start is reading Howard Johnson's books, like "High-Speed Digital Design, A Handbook of Black Magic."
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

你好奥斯汀，为什么用工具从最小周期减去总峰值到峰值抖动的一半。
不应该是总峰值到峰值的抖动吗？从上面提到的问题来看，10 ns  -  100 ps = 9.9 ns.Thank you



以下为原文

Hello Austin,
Why is one half of the total peak to peak jitter subtracted from the minimum period by tools. Should'nt it be the total peak to peak jitter?
From the question asked above, 10 ns - 100 ps = 9.9 ns.

Thank you

R，
它是1/2，因为出于关键路径的目的，由于抖动，时钟可能更早到达。
我们不关心时钟边缘是否会延迟 - 这只是更松弛（好）。
除了抖动之外，为了安全起见，人们通常会使用一些保护带（所以没有路径没有松弛）。
过去，这是因为它们没有包含抖动。
现在，在包含抖动的情况下，所包含的额外余量与您能够预测最坏情况系统抖动的能力有关。
如果你不知道，你怎么能应用任何价值？
Austin Lesea主要工程师Xilinx San Jose



以下为原文

r,
 
It is 1/2 because for purposes of the critical path, the clock could arrive earlier, due to jitter.  We do not care if the clock edge atrrives later -- that is just more slack (good).
 
In addition to the jitter, people usually apply some guard band (so no path has zero slack) just to be safe.  In the past, this was because they did not include the jitter.  Now, with the jitter included, the extra slack included is related to how well you are able to predict the worst case system jitter.  If you do not know it, how can you apply any value at all?
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose