具有两个从端口的AXI Cros***ar v2.1的数据断言

你好，
当使用两个从端口S0和S1时，我在SAMD中遇到了AXI Cros***ar v2.1 Vivado 2013.3的一些问题。
一旦只使用一个从端口S0，一切正常，但是一旦使用另一个从端口S1，我就会出现读取访问的奇怪行为。
例如，在读取序列（如S0-> S1）之后，对于每次后续读取，相应的数据在一个额外的时钟周期后被置位，从而导致与有效信号的置位不匹配，有效信号现在在数据之前的一个时钟周期被置位。
模拟根本没有显示这种行为，我只是通过使用Chipscope看到它，另外它在SASD模式下不会发生。
亲切的问候
斯特芬



以下为原文

Hello,

I have some issues with the AXI Cros***ar v2.1 Vivado 2013.3 in SAMD when using two Slave Ports S0 and S1. As long as only one Slave Port S0 is used everything works just fine, but as soon as the other Slave Port S1 is used I get strange behaviour for read access. For Example after a read sequence like S0->S1, for every subsequent Read the corresponding data is asserted after one additional clock cycle, causing a mismatch with the assertion of the valid signal, which is now asserted one clock cycle before the data.

Simulation didn't show this behaviour at all, I saw it only by using Chipscope, additionally it does not happen in SASD mode.

Kind Regards
Steffen