Soure an entire OUT packet without host communication

我试着完成了源数据包到从属FIFO接口。
管4在手动模式下，从主机的所有数据包需要提交发送到外围设备（FPGA）。
这工作很好，但我需要交流与互动的FPGA无主。
我按照示例代码从TRM。
我看到新的资源包来了FPGA只有当数据包从主机的pipe4收到。
我错过了什么？
在TDyPrase:
如果（ep24fifoflgs &；0x20）{ syncdelay；/ / fiforeset = 0x80；/ / NAK所有封包。从主机syncdelay；/ / fiforeset = 0x84；//事先EP4缓冲器CPU领域syncdelay；/ / ep4fifobuf [ 0 ] = 0；//创建新资源包。数据syncdelay；/ / ep4bch = 0x00；SYNCDELAY；/ / ep4bcl = 0x40；/ /提交新来源的口袋。接口的FIFO /当心”对“中立的缓冲区syncdelay左；/ / outpktend = 0x84；/ /跳过空袋。（二袋。）/ /注：核心不允许封包。走出序列syncdelay；/ / fiforeset = 0x00；//释放“NAK”}



     以下为原文
  I try source a complete OUT packet to the slave fifo interface.
    Pipe 4 is in manual mode and all packets from the host need to be commited to send out to the peripheral device (FPGA).
    This works fine, but i need to commnicate with the FPGA without host interaction.
    I follow the example code from the TRM.
    I see the new sourced packet comming out to the FPGA only when a packet is received on pipe4 from the host.
    What do I missing here?
    in TD_POLL:
         if( EP24FIFOFLGS & 0x20 ) {
        SYNCDELAY; //
        FIFORESET = 0x80; // nak all OUT pkts. from host
        SYNCDELAY; //
        FIFORESET = 0x84; // advance all EP4 buffers to cpu domain
        SYNCDELAY; //
        EP4FIFOBUF[0] = 0x0; // create newly sourced pkt. data
        SYNCDELAY; //
        EP4BCH = 0x00;
        SYNCDELAY; //
        EP4BCL = 0x40; // commit newly sourced pkt. to interface fifo
        // beware of "left over" uncommitted buffers
        SYNCDELAY; //
        OUTPKTEND = 0x84; // skip uncommitted pkt. (second pkt.)
        // note: core does not allow pkts. to get out of sequence
        SYNCDELAY; //
        FIFORESET = 0x00; // release "nak all"
    }