怎么使用synplify从ISE 14.5中为coregen核心进行合成

嗨，我认为这仍然可以作为xilinx问题（而不是synplify pro问题），因为我在xilinx ISE 14.5中使用synplify pro仅用于合成。
所以这里......
我在verilog编码。
我使用xilinx coregen制作了一个小型的fifo，并将其包含在我的verilog设计中。
我使用synplify pro运行综合，它没有错误地完成。
但是，当我查看synplify日志文件时，它会显示一条警告 -
“为空模块创建黑盒子”，我没有看到synplify为fifo核心调用xilinxcorelib（但它确实搜索其他libs，如unisim，simprim等）
此外，当我使用xilinx ISE 14.5实现设计（即运行translate / map / P＆amp; R）时，也没有任何错误，但在xilinx设计摘要中，我得到警告，表明“所有输入信号到fifo
核心已被删除“。
我的问题 -
1）使用synplify进行合成时，是否有使用/实例化xilinx coregen内核的特殊方法？
2）如何将synplify指向xilinxcorelib（如果需要）？
3）我需要在synplify中包含核心的.ngc文件还是自动发生？
4）警告好吗？
5）我可能错过了什么？
我添加了synplify日志（main_compiler.doc）文件以供参考。
谢谢你的投入。
ž。
main_compiler.doc 6 KB



以下为原文

Hi, I think this may still qualify as a xilinx question (and not a synplify pro question) because i am using synplify pro from within xilinx ISE 14.5 ONLY FOR SYNTHESIS. So here goes ...

i'm coding in verilog. i made a small fifo using xilinx coregen and included it in my verilog design. i ran synthesis using synplify pro and it went through without errors. however, when i look at the synplify log file, it shows a warning saying -

"creating black box for empty module " and i don't see synplify calling the xilinxcorelib for the fifo core (but it does search for other libs like unisim, simprim etc.)

furthermore, when i implement the design (i.e. run translate/map/P&R) using xilinx ISE 14.5, that also goes through without any errors but in the xilinx design summary i get warnings which indicate that "all the input signals to the fifo core have been removed".

my questions -

1) is there any special method to use/instantiate xilinx coregen cores while synthesizing using synplify?
2) how do i point synplify to the xilinxcorelib (if needed)?
3)do i need to include the core's .ngc file inside synplify or does it happen automatically?
4) are the warnings ok?
5) anything that i may have missed out?

ive added the synplify log (main_compiler.doc) file for reference.

thanks for your inputs.

z.

            main_compiler.doc ‏6 KB

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