如何为XTP148制作ISE项目

嗨，
有一个implement.bat，您可以运行它来直接生成位文件。
但是，位文件已存在于ready_to_download目录中，您可以直接使用该目录。
但是，如果您想知道项目的组装方式，可以检查实现目录中的planAhead_rdn.tcl文件。
您需要添加示例设计目录中的所有verilog文件和ucf文件以及实现目录中的.ngc文件，并尝试生成设计。
这应该可以帮助您生成比特流。
如果您仍然遇到问题并在此处发布错误，请告知我，以防您在实施时遇到错误。
谢谢，AnirudhPS：请将此标记作为答案，以防它有助于解决您的问题。如果帖子引导您找到解决方案，请给予赞誉。
在原帖中查看解决方案



以下为原文

Hi,
 
There is an implement.bat  which you can run to directly generate the bit file. However the bit file is already present in the ready_to_download directory which you can directly use.
 
However if you want to know how the project has been assembled you can check the planAhead_rdn.tcl file in the implement directory. You need to add all the verilog files and ucf files from the example design directory and also the .ngc file from the implement directory and try generating the design. This should help you generate the bitstream.
 

Let me know if you still face problem and post the error here in case you are getting an error while implementing.
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.View solution in original post

嗨，
解压缩文件后，您将观察下面快照中指定的文件。
现在打开ISE并选择突出显示的文件（ISE项目（.xise））以在ISE中打开项目。
谢谢
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以下为原文

Hi Xun,
 
After unzipping the files, you will observe the files specified in the below snapshot.

 
Now Open ISE and select the highlighted file (ISE project (.xise)) to open the project in ISE.
 
Thanks
--------------------------------------------------------------------------------------------
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你好Vuppala，
非常感谢您的回复。
您找到的ISE项目文件位于“vc707_ethernet  coregen_outputs ”目录中，不是吗？
我想要实现的设计是目录“vc707_ethernet  tri_mode_eth_mac_v5_2_with_sgmii  example_design ”中的示例设计。
我尝试创建一个新的ISE项目，将所有源文件添加到它，但我无法合成它。
您知道如何将此示例设计作为ISE项目打开吗？
迅



以下为原文

Hello Vuppala,
Thank you very much for your reply. The ISE project file you found is in the “vc707_ethernetcoregen_outputs” directory, isn’t it? The design I would like to implement is the example design in the directory “vc707_ethernettri_mode_eth_mac_v5_2_with_sgmiiexample_design”. I tried creating a new ISE project, adding all the source files to it, but I just could not synthesize it. Do you know how to open this example design as an ISE project?
Xun

嗨，
有一个implement.bat，您可以运行它来直接生成位文件。
但是，位文件已存在于ready_to_download目录中，您可以直接使用该目录。
但是，如果您想知道项目的组装方式，可以检查实现目录中的planAhead_rdn.tcl文件。
您需要添加示例设计目录中的所有verilog文件和ucf文件以及实现目录中的.ngc文件，并尝试生成设计。
这应该可以帮助您生成比特流。
如果您仍然遇到问题并在此处发布错误，请告知我，以防您在实施时遇到错误。
谢谢，AnirudhPS：请将此标记作为答案，以防它有助于解决您的问题。如果帖子引导您找到解决方案，请给予赞誉。



以下为原文

Hi,
 
There is an implement.bat  which you can run to directly generate the bit file. However the bit file is already present in the ready_to_download directory which you can directly use.
 
However if you want to know how the project has been assembled you can check the planAhead_rdn.tcl file in the implement directory. You need to add all the verilog files and ucf files from the example design directory and also the .ngc file from the implement directory and try generating the design. This should help you generate the bitstream.
 

Let me know if you still face problem and post the error here in case you are getting an error while implementing.
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.