如何合并两个FIFO18E1在一个36Kb的blockram中

嗨，OK。
您是否在地图报告文件.mrp / .map中检查资源利用率？
是否相同？检查http://www.xilinx.com/support/documentation/user_guides/ug190.pdf的第130页。对于要包装到同一站点的两个ramb18，他们可能需要有一些常见的信号，如时钟等。
可以使用BEL UPPER / LOWER约束将两个RAMB18放置在同一RAMB36位置：inst“my_ramb18”LOC = RAMB36_X0Y0 |
BEL = UPPERinst“my_ramb18”LOC = RAMB36_X0Y0 |
BEL = LOWER如果工具没有将ramb18放入同一个站点，可以使用约束来强制工具执行此操作，如果它们满足所有必要的规则。谢谢，Deepika。
谢谢，迪皮卡.----------------------------------------------
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以下为原文

Hi,

Ok. Did you check resource utilization in map report file .mrp/.map? Is it the same?

Check page-130 of http://www.xilinx.com/support/documentation/user_guides/ug190.pdf

For two ramb18 to be packed in to same site they may need to have some common signals like clock etc.

Two RAMB18s can be placed in the same RAMB36 location by using the BEL UPPER/LOWER constraint:

inst ”my_ramb18” LOC = RAMB36_X0Y0 | BEL = UPPER
inst ”my_ramb18” LOC = RAMB36_X0Y0 | BEL = LOWER

If the tool is not placing the ramb18 in to the same site, the constraints can be used to force the tool to do this if they satisfy all the rules necessary.

Thanks,
Deepika.Thanks,
Deepika.
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嗨，
2个18Kb FIFO被占用还是36-Kb？
请参阅UG768的Page-58端口配置详细信息。
FIFO18E的数据宽度是多少，您能显示实例化和合成报告吗？
问候，
Vanitha。
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以下为原文

Hi,
 
2 18Kb FIFOs occupied or 36-Kb ?
Please see Page - 58 port configuration deatils of UG768.
What is the data width of FIFO18E, can you show your instantiation and syntheiss report?
 
 
Regards,
Vanitha.
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嗨，
您可以尝试将FIFO同时锁定到同一个BRAM站点，如下所示（在UCF中，如果您使用的是ISE）：
INST“fifo_inst1”LOC = RAMB36_XxYy;
INST“fifo_inst2”LOC = RAMB36_XxYy;
谢谢，
迪皮卡。
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以下为原文

Hi,
 
You may try locking both the FIFO's to the same BRAM site as below (in UCF, if you are using ISE):
 
INST "fifo_inst1" LOC = RAMB36_XxYy;
INST "fifo_inst2" LOC = RAMB36_XxYy;
 
Thanks,
Deepika.
Thanks,
Deepika.
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None


以下为原文

First let me reply to vemulad: I am... afraid to do this. Won't this mess up the great automatic map, translate and route processes? This is a uni project in which I don't really do more than synthesize. 
 
Now to vsrunga:
This is the file where I describe a single (16-bit, by the way) queue:
 
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;LIBRARY UNISIM;USE UNISIM.VCOMPONENTS.ALL;LIBRARY UNIMACRO;USE UNIMACRO.VCOMPONENTS.ALL;entity fifo_bram_16bit_sync isPort( clk : in  STD_LOGIC;reset : in  STD_LOGIC;we,re :in STD_LOGIC; --write/read enabledata_in :in  STD_LOGIC_VECTOR(15  downto 0);data_out :out STD_LOGIC_VECTOR(15 downto 0);--Write pointerwp_out : out STD_LOGIC_VECTOR(9  downto 0);empty_out, full_out:out STD_LOGIC);end fifo_bram_16bit_sync;architecture instantiation of fifo_bram_16bit_sync issignal dummy: std_logic_vector(9 downto 0); -- Useless, but rdcount does not work with "open"beginFIFO_SYNC_MACRO_inst : FIFO_SYNC_MACRO   generic map (      DEVICE => "7SERIES",            -- Target Device: "VIRTEX5, "VIRTEX6", "7SERIES"       ALMOST_FULL_OFFSET => X"0080",  -- Sets almost full threshold      ALMOST_EMPTY_OFFSET => X"0080", -- Sets the almost empty threshold      DATA_WIDTH => 16,   -- Valid values are 1-72 (37-72 only valid when FIFO_SIZE="36Kb")      FIFO_SIZE => "18Kb"            -- Target BRAM, "18Kb" or "36Kb" )   port map (      ALMOSTEMPTY => open,   -- 1-bit output almost empty      ALMOSTFULL => open,     -- 1-bit output almost full      DO => data_out,-- Output data, width defined by DATA_WIDTH parameter      EMPTY => empty_out,-- 1-bit output empty      FULL => full_out,  -- 1-bit output full      RDCOUNT => dummy,  -- Output read count, width determined by FIFO depth      RDERR => open,  -- 1-bit output read error      WRCOUNT => wp_out,  -- Output write count, width determined by FIFO depth      WRERR => open,   -- 1-bit output write error      CLK => clk,      -- 1-bit input clock      DI => data_in,   -- Input data, width defined by DATA_WIDTH parameter      RDEN => re,        -- 1-bit input read enable      RST => reset,     -- 1-bit input reset      WREN => we       -- 1-bit input write enable   );   -- End of FIFO_SYNC_MACRO_inst instantiationend instantiation; And here's the file where I instantiate two of the queues as components. Note that this is highly incomplete, but I just needed to see how many bram resources it would take.
LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.NUMERIC_STD.ALL;entity mapped_queue isPort( clk : in  STD_LOGIC;reset : in  STD_LOGIC;data_strobe : in  STD_LOGIC;data_re :in  STD_LOGIC;ps_re :in  STD_LOGIC;data_in :in  STD_LOGIC_VECTOR(7  downto 0);data_out :out STD_LOGIC_VECTOR(15 downto 0);--18Kb 32-bit word has address of 9ps_out : out STD_LOGIC_VECTOR(15  downto 0);empty_out, full_out:out STD_LOGIC);end mapped_queue;architecture mixed of mapped_queue iscomponent input_compactor_8to16bit isPort( clk : in  STD_LOGIC;reset : in  STD_LOGIC;we_in:in STD_LOGIC;we_out : out STD_LOGIC;data_in :in  STD_LOGIC_VECTOR(7  downto 0);data_out :out STD_LOGIC_VECTOR(15 downto 0));end component;component fifo_bram_16bit_sync isPort( clk : in  STD_LOGIC;reset : in  STD_LOGIC;we,re :in STD_LOGIC; --write/read enabledata_in :in  STD_LOGIC_VECTOR(15  downto 0);data_out :out STD_LOGIC_VECTOR(15 downto 0);wp_out : out STD_LOGIC_VECTOR(9  downto 0); --write pointerempty_out, full_out:out STD_LOGIC);end component;--Wires(used in concurrent statements)signal we_compactor_to_dataqueue: STD_LOGIC;signal data_compactor_to_dataqueue: STD_LOGIC_VECTOR(15 downto 0);signal dataqueue_wp: STD_LOGIC_VECTOR(9  downto 0);signal data_psqueue_to_pshead: STD_LOGIC_VECTOR(15 downto 0);--Registers(used in process withing if(rising_edge(clk)) then.. block )signal last_strobe: STD_LOGIC;signal last_ps_re: STD_LOGIC;signal ps_head_empty: STD_LOGIC;signal ps_head: STD_LOGIC_VECTOR(15 downto 0);beginDATA_QUEUE_INPUT_COMPACTOR: input_compactor_8to16bitport map(clk=> clk,reset=> reset,we_in=> data_strobe,we_out=> we_compactor_to_dataqueue,data_in=> data_in,data_out=> data_compactor_to_dataqueue);DATA_QUEUE: fifo_bram_16bit_syncport map(clk=> clk,reset=> reset,we=> we_compactor_to_dataqueue,re=> data_re,data_in=> data_psqueue_to_pshead,data_out=> data_out,wp_out=> dataqueue_wp,empty_out=> empty_out,full_out=> full_out);PS_QUEUE: fifo_bram_16bit_sync --Packet Size queueport map(clk=> clk,reset=> reset,we=> '1',re=> '1',data_in=> X"FFFF",data_out=> data_psqueue_to_pshead,wp_out=> open,empty_out=> open,full_out=> open);--process(clk)--begin--if(rising_edge(clk)) then--if(reset='1') then--ps_head_empty <= '1';--else--if(ps_re='1' and ps_head_empty='0') then--if(last_ps_re='0') then----null;--end if; --reset if--last_strobe <= data_strobe;--last_ps_re <= psize_re;--end if; -- clk if--end process;end mixed; I now give the synthesis device utilization summary:
Device utilization summary:---------------------------Selected Device : 7k325tfbg676-2 Slice Logic Utilization:  Number of Slice Registers:               1  out of  407600     0%   Number of Slice LUTs:                    2  out of  203800     0%      Number used as Logic:                 2  out of  203800     0%  Slice Logic Distribution:  Number of LUT Flip Flop pairs used:      3   Number with an unused Flip Flop:       2  out of      3    66%     Number with an unused LUT:             1  out of      3    33%     Number of fully used LUT-FF pairs:     0  out of      3     0%     Number of unique control sets:         1IO Utilization:  Number of IOs:                          47 Number of bonded IOBs:                  22  out of    400     5%  Specific Feature Utilization: Number of Block RAM/FIFO:                2  out of    445     0%      Number using FIFO only:               2 Number of BUFG/BUFGCTRLs:                1  out of     32     3%   
 

嗨，OK。
您是否在地图报告文件.mrp / .map中检查资源利用率？
是否相同？检查http://www.xilinx.com/support/documentation/user_guides/ug190.pdf的第130页。对于要包装到同一站点的两个ramb18，他们可能需要有一些常见的信号，如时钟等。
可以使用BEL UPPER / LOWER约束将两个RAMB18放置在同一RAMB36位置：inst“my_ramb18”LOC = RAMB36_X0Y0 |
BEL = UPPERinst“my_ramb18”LOC = RAMB36_X0Y0 |
BEL = LOWER如果工具没有将ramb18放入同一个站点，可以使用约束来强制工具执行此操作，如果它们满足所有必要的规则。谢谢，Deepika。
谢谢，迪皮卡.----------------------------------------------
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以下为原文

Hi,

Ok. Did you check resource utilization in map report file .mrp/.map? Is it the same?

Check page-130 of http://www.xilinx.com/support/documentation/user_guides/ug190.pdf

For two ramb18 to be packed in to same site they may need to have some common signals like clock etc.

Two RAMB18s can be placed in the same RAMB36 location by using the BEL UPPER/LOWER constraint:

inst ”my_ramb18” LOC = RAMB36_X0Y0 | BEL = UPPER
inst ”my_ramb18” LOC = RAMB36_X0Y0 | BEL = LOWER

If the tool is not placing the ramb18 in to the same site, the constraints can be used to force the tool to do this if they satisfy all the rules necessary.

Thanks,
Deepika.Thanks,
Deepika.
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我会记住你的帖子。
也许我应该尝试实例化890以确定它是否合适。
无论如何，我认为这是档案。
谢谢！



以下为原文

I will keep your post in mind. Maybe I should try to instatiate 890 to see if it fits. At any rate, I consider this as archive. Thanks!

我不认为TRAM36中的fifo逻辑是重复的。
据我所知，你可以做BRAM36，BRAM18 + BRAM18，BRAM18 + FIFO18或FIFO36。



以下为原文

 I don't think the fifo logic is duplicated in the BRAM36.  From what I recall, you could do BRAM36, BRAM18+BRAM18, BRAM18+FIFO18, or FIFO36.

嗨克里斯，
谢谢你的纠正。
在7系列器件中，每个Block RAM Tile只有一个FIFO逻辑可用，因此只能容纳一个FIFO36E1或一个FIFO18E1。
但是，如果FIFO18E1占用Block RAM Tile，则该磁贴仍然可以容纳RAMB18E1。
乔治，
对不起最初我以为你正在使用FIFO核心（内部使用BRAM原语），我刚看到你使用FIFO_SYNC_MACRO的代码。
正如克里斯指出的那样，这是不可能的。
Page-67 of xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf显示了BRAM / FIFIO原语的合法组合。
问候，
迪皮卡。
谢谢，迪皮卡.----------------------------------------------
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以下为原文

Hi Chris,
 
Thanks for the correction.
 
In 7-series devices each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1.
 
George,
 
Sorry Initially I thought you are using FIFO core (which uses BRAM primitives internally), I just saw the code where you were using FIFO_SYNC_MACRO. So as Chris pointed out, this is not possible. 
 
Page-67 of http://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf shows legal combinations of BRAM/FIFIO primitives.
 
Regards,
Deepika.
Thanks,
Deepika.
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